Further Characterisation of Digital Pixel Test Structures Implemented in a 65 nm CMOS Process

TL;DR

The paper evaluates Digital Pixel Test Structure (DPTS) sensors implemented in Tower Partners 65 nm CMOS to support the ALICE ITS3 goals of ultra-low mass and low power. It combines laboratory measurements, fluorescence X-ray linearity tests, and beam tests to characterize low-power performance, ionising irradiation tolerance, fake-hit rates, and response to inclined tracks, including ToT calibration shifts and annealing effects. The results show that pixel-matrix power around the ITS3 target preserves high efficiency (>99%) and low fake-hit rates, with annealing and hot-pixel masking mitigating radiation- and noise-induced degradation; fluorescence and beam data confirm front-end linearity up to 28.5 keV and robust charge collection under irradiation. These findings inform the ITS3 ER1 development and support the feasibility of wafer-scale, curved MAPS sensors with improved power and performance budgets.

Abstract

The next generation of MAPS for future tracking detectors will have to meet stringent requirements placed on them. One such detector is the ALICE ITS3 that aims to be very light at 0.07% X/X$_{0}$ per layer and have a low power consumption in the active area of 40 mW/cm$^{2}$ by implementing wafer-scale MAPS bent into cylindrical half layers. To address these challenging requirements, the ALICE ITS3 project, in conjunction with the CERN EP R&D on monolithic pixel sensors, proposed the Tower Partners Semiconductor Co. 65 nm CMOS process as the starting point for the sensor. After the initial results confirmed the detection efficiency and radiation hardness, the choice of the technology was solidified by demonstrating the feasibility of operating MAPS in low-power consumption regimes, < 50 mW/cm$^{2}$, while maintaining high-quality performance. This was shown through a detailed characterisation of the Digital Pixel Test Structure (DPTS) prototype exposed to X-rays and ionising beams, and the results are presented in this article. Additionally, the sensor was further investigated through studies of the fake-hit rate, the linearity of the front-end in the range 1.7-28 keV, the performance after ionising irradiation, and the detection efficiency of inclined tracks in the range 0-45$^\circ$.

Figures (21)

• Figure 1: The threshold RMS and fake-hit rate vs. threshold (top) and the noise mean and fake-hit rate vs. threshold (bottom) at different $I_{bias}$ values. At each $I_{bias}$, the chip bias parameters were optimised, except $I_{bias}=\qty{100}{\nA}$, which is left at the "nominal" settings for comparison.
• Figure 2: The threshold RMS and fake-hit rate vs. threshold (left) and the noise mean and fake-hit rate vs. threshold (right) at varying $V_{sub}$ values at $I_{bias}=\qty{10}{\nA}$. At each $V_{sub}$, the chip bias parameters were optimised.
• Figure 3: Left: the threshold mean and fake-hit rate vs. ionising radiation dose at a constant $V_{casb}$. Right: the threshold RMS and fake-hit rate vs. ionising radiation dose at a threshold tuned to 125 for two chips irradiated to different dose levels, 10 and 100, at different rates.
• Figure 4: Left: the threshold mean and fake-hit rate vs. the time since the end of the irradiation at a constant $V_{casb}$ for a chip with a total dose of 500. Right: the threshold RMS and fake-hit rate vs. the time since the end of the irradiation at a threshold tuned to 125 for a chip with a total dose of 100. The red boxes indicate the period during which the sensor underwent irradiation.
• Figure 5: Measured $^{55}$Fe spectra of single pixel clusters for different levels of ionising irradiation: non-irradiated, 10, 100, 500 and 5.