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LaZagna: An Open-Source Framework for Flexible 3D FPGA Architectural Exploration

Ismael Youssef, Hang Yang, Cong Hao

TL;DR

LaZagna addresses the lack of open, end-to-end tools for 3D FPGA exploration by providing an automated framework that spans architectural specification, synthesizable RTL generation, and bitstream production. It introduces a large, configurable design space including vertical interconnect types, 3D SB/CB patterns, and heterogeneous layer configurations, and integrates with OpenFPGA and VTR to enable full physical design flows. Five case studies demonstrate that 3D FPGA architectures can reduce critical path delay and wirelength compared with 2D baselines, while highlighting trade-offs in via density and routing runtime. The framework's open-source nature and end-to-end validation capability offer a practical platform for exploring 3D packaging technologies and guiding future FPGA architectures and toolchains.

Abstract

While 3D IC technology has been extensively explored for ASICs, their application to FPGAs remains limited. Existing studies on 3D FPGAs are often constrained to fixed prototypes, narrow architectural templates, and simulation-only evaluations. In this work, we present LaZagna, the first open-source framework for automated, end-to-end 3D FPGA architecture generation and evaluation. LaZagna supports high-level architectural specification, synthesizable RTL generation, and bitstream production, enabling comprehensive validation of 3D FPGA designs beyond simulation. It significantly broadens the design space compared to prior work by introducing customizable vertical interconnect patterns, novel 3D switch block designs, and support for heterogeneous logic layers. The framework also incorporates practical design constraints such as inter-layer via density and vertical interconnect delay. We demonstrate the capabilities of LaZagna by generating synthesizable RTL that can be taken through full physical design flows for fabric generation, along with functionally correct bitstreams. Furthermore, we conduct five case studies that explore various architectural parameters and evaluate their impact on wirelength, critical path delay, and routing runtime. These studies showcase the framework's scalability, flexibility, and effectiveness in guiding future 3D FPGA architectural and packaging decisions. LaZagna is fully open-source and available on GitHub.

LaZagna: An Open-Source Framework for Flexible 3D FPGA Architectural Exploration

TL;DR

LaZagna addresses the lack of open, end-to-end tools for 3D FPGA exploration by providing an automated framework that spans architectural specification, synthesizable RTL generation, and bitstream production. It introduces a large, configurable design space including vertical interconnect types, 3D SB/CB patterns, and heterogeneous layer configurations, and integrates with OpenFPGA and VTR to enable full physical design flows. Five case studies demonstrate that 3D FPGA architectures can reduce critical path delay and wirelength compared with 2D baselines, while highlighting trade-offs in via density and routing runtime. The framework's open-source nature and end-to-end validation capability offer a practical platform for exploring 3D packaging technologies and guiding future FPGA architectures and toolchains.

Abstract

While 3D IC technology has been extensively explored for ASICs, their application to FPGAs remains limited. Existing studies on 3D FPGAs are often constrained to fixed prototypes, narrow architectural templates, and simulation-only evaluations. In this work, we present LaZagna, the first open-source framework for automated, end-to-end 3D FPGA architecture generation and evaluation. LaZagna supports high-level architectural specification, synthesizable RTL generation, and bitstream production, enabling comprehensive validation of 3D FPGA designs beyond simulation. It significantly broadens the design space compared to prior work by introducing customizable vertical interconnect patterns, novel 3D switch block designs, and support for heterogeneous logic layers. The framework also incorporates practical design constraints such as inter-layer via density and vertical interconnect delay. We demonstrate the capabilities of LaZagna by generating synthesizable RTL that can be taken through full physical design flows for fabric generation, along with functionally correct bitstreams. Furthermore, we conduct five case studies that explore various architectural parameters and evaluate their impact on wirelength, critical path delay, and routing runtime. These studies showcase the framework's scalability, flexibility, and effectiveness in guiding future 3D FPGA architectural and packaging decisions. LaZagna is fully open-source and available on GitHub.
Paper Structure (25 sections, 11 figures, 5 tables)

This paper contains 25 sections, 11 figures, 5 tables.

Table of Contents

  1. Introduction
  2. Previous Work and Limitations
  3. Tool Workflow
  4. 3D FPGA Architectural Parameters
  5. Vertical Connection Types (Fig. \ref{['fig:tool_parameters_a']})
  6. 3D SB Placement Locations (Fig. \ref{['fig:tool_parameters_e']})
  7. 3D Switch Block Connection Patterns (Fig. \ref{['fig:tool_parameters_b']})
  8. Vertical Connection Delay Ratio (Fig. \ref{['fig:tool_parameters_c']})
  9. Layer Count and Heterogeneity (Fig. \ref{['fig:tool_parameters_d']})
  10. All Standard 2D FPGA Parameters
  11. 3D Fabric Routing Resource Graph Creation
  12. 3D FPGA Architecture RTL Generation
  13. Benchmark Logic Synthesis, Placement, and Routing
  14. Bitstream Generation
  15. Tool Output
  16. ...and 10 more sections

Figures (11)

  • Figure 1: LaZagna overview. It has two parallel flows: 1. 3D FPGA fabric RTL generation 2. benchmark bitstream generation.
  • Figure 2: LaZagna input parameters.
  • Figure 3: Implementation of different layer heterogeneity 3D FPGAs onto a Xilinx Virtex Ultrascale+ using RTL generated by LaZagna
  • Figure 4: Physical implementation of a two-layer homogeneous 3D-SB FPGA. Routing closure is achieved, verifying LaZagna's RTL generation.
  • Figure 5: Runtime breakdown of LaZagna on various Grid Sizes.
  • ...and 6 more figures