PUDTune: Multi-Level Charging for High-Precision Calibration in Processing-Using-DRAM

TL;DR

PUDTune addresses the reliability bottleneck of Processing-Using-DRAM by introducing a high-precision offset calibration that exploits multi-level charge states. By combining differing numbers of Frac operations across calibration rows, it achieves a wide and fine-grained offset repertoire within few available rows, substantially reducing error-prone columns. The approach reduces the error-prone column ratio from about $46.6\%$ to $3.3\%$ and boosts MAJ5, 8-bit addition, and 8-bit multiplication throughput by approximately $1.81\times$, $1.88\times$, and $1.89\times$, respectively, with only $0.6\%$ capacity overhead, and demonstrates robust thermal and time-based reliability. This work enables practical, high-precision analog computing within unmodified DRAM, improving the viability of PUD for real-world workloads.

Abstract

Recently, practical analog in-memory computing has been realized using unmodified commercial DRAM modules. The underlying Processing-Using-DRAM (PUD) techniques enable high-throughput bitwise operations directly within DRAM arrays. However, the presence of inherent error-prone columns hinders PUD's practical adoption. While selectively using only error-free columns would ensure reliability, this approach significantly reduces PUD's computational throughput. This paper presents PUDTune, a novel high-precision calibration technique for increasing the number of error-free columns in PUD. PUDTune compensates for errors by applying pre-identified column-specific offsets to PUD operations. By leveraging multi-level charge states of DRAM cells, PUDTune generates fine-grained and wide-range offset variations despite the limited available rows. Our experiments with DDR4 DRAM demonstrate that PUDTune increases the number of error-free columns by 1.81$\times$ compared to conventional implementations, improving addition and multiplication throughput by 1.88$\times$ and 1.89$\times$ respectively.

Figures (6)

• Figure 1: Comparison of MAJ5 execution with $8$-row SiMRA in a DRAM subarray. (a) Conventional method. (b) PUDTune.
• Figure 2: (a) DRAM organization. (b) PUD operations.
• Figure 3: Comparison of offset variations for different Frac count configurations. (a) $\text{T}_{0, 0, 0}$: No Frac operations applied. (b) $\text{T}_{2, 2, 2}$: Two Frac operations applied to all three rows. (c) $\text{T}_{2, 1, 0}$: Two, one, and zero Frac operations applied to the first, second, and third rows, respectively.
• Figure 4: Experimental setup.
• Figure 5: MAJ5 performance sensitivity to Frac times.