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Enhancing Reinforcement Learning for the Floorplanning of Analog ICs with Beam Search

Sandro Junior Della Rovere, Davide Basso, Luca Bortolussi, Mirjana Videnovic-Misic, Husni Habal

TL;DR

This work tackles analog IC floorplanning under multiple objectives by augmenting a pre-existing RL-based planner with a beam-search-based inference process (BS-RL). The approach builds a search tree during inference, uses a congestion-aware evaluation to prune candidates, and preserves the original policy to avoid retraining or GPU reliance, while enabling adjustable area and routing trade-offs. Experimental results on 130 nm ICs show BS-RL yields substantial improvements over standard RL in dead space, HPWL, and routing congestion, often matching state-of-the-art fine-tuning performance without GPUs. The method delivers a practical, scalable, CPU-friendly path toward routing-friendly, multi-objective analog floorplans with robust generalization, and points to future integration with detailed routing feedback and post-layout verification.

Abstract

The layout of analog ICs requires making complex trade-offs, while addressing device physics and variability of the circuits. This makes full automation with learning-based solutions hard to achieve. However, reinforcement learning (RL) has recently reached significant results, particularly in solving the floorplanning problem. This paper presents a hybrid method that combines RL with a beam (BS) strategy. The BS algorithm enhances the agent's inference process, allowing for the generation of flexible floorplans by accomodating various objective weightings, and addressing congestion without without the need for policy retraining or fine-tuning. Moreover, the RL agent's generalization ability stays intact, along with its efficient handling of circuit features and constraints. Experimental results show approx. 5-85% improvement in area, dead space and half-perimeter wire length compared to a standard RL application, along with higher rewards for the agent. Moreover, performance and efficiency align closely with those of existing state-of-the-art techniques.

Enhancing Reinforcement Learning for the Floorplanning of Analog ICs with Beam Search

TL;DR

This work tackles analog IC floorplanning under multiple objectives by augmenting a pre-existing RL-based planner with a beam-search-based inference process (BS-RL). The approach builds a search tree during inference, uses a congestion-aware evaluation to prune candidates, and preserves the original policy to avoid retraining or GPU reliance, while enabling adjustable area and routing trade-offs. Experimental results on 130 nm ICs show BS-RL yields substantial improvements over standard RL in dead space, HPWL, and routing congestion, often matching state-of-the-art fine-tuning performance without GPUs. The method delivers a practical, scalable, CPU-friendly path toward routing-friendly, multi-objective analog floorplans with robust generalization, and points to future integration with detailed routing feedback and post-layout verification.

Abstract

The layout of analog ICs requires making complex trade-offs, while addressing device physics and variability of the circuits. This makes full automation with learning-based solutions hard to achieve. However, reinforcement learning (RL) has recently reached significant results, particularly in solving the floorplanning problem. This paper presents a hybrid method that combines RL with a beam (BS) strategy. The BS algorithm enhances the agent's inference process, allowing for the generation of flexible floorplans by accomodating various objective weightings, and addressing congestion without without the need for policy retraining or fine-tuning. Moreover, the RL agent's generalization ability stays intact, along with its efficient handling of circuit features and constraints. Experimental results show approx. 5-85% improvement in area, dead space and half-perimeter wire length compared to a standard RL application, along with higher rewards for the agent. Moreover, performance and efficiency align closely with those of existing state-of-the-art techniques.
Paper Structure (10 sections, 7 equations, 3 figures, 1 table)

This paper contains 10 sections, 7 equations, 3 figures, 1 table.

Table of Contents

  1. Introduction
  2. Problem Definition
  3. Beam Search Boosted RL Floorplanning
  4. Beam Search
  5. Reinforcement Learning (RL)
  6. Beam Search and Reinforcement Learning: BS-RL
  7. Experimental Results and Discussion
  8. Experiment Details
  9. Comparison Against Baselines
  10. Conclusions

Figures (3)

  • Figure 1: High level schematic of the automated layout pipeline presented in basso_effective_2025. The contributions of this paper are highlighted in green.
  • Figure 2: \ref{['fig:bs_example']} OTA-2 graph representation from basso_effective_2025. Pink edges represent alignment constraints. \ref{['fig:bs_example']} BS-RL state tree: in step $k\!=\!1$, rectangular module $b_1$ is placed in different ways to form level $1$, $b_2$ is placed in step $k\!=\!2$. \ref{['fig:bs_example']} BS is applied after completion of level $2$, with $\beta=4$.
  • Figure 3: Examples of outputs of BS-RL ($k=5$, $\epsilon=0.7$, $\beta=10$), applied to the OTA-2 instance. From left to right, the first two show what happens when setting the congestion threshold to $\infty$ or $0.1$, and the last two illustrate the result of choosing $\alpha=1$ and $\delta=1000$, and vice-versa. Slight manual refinement would be needed before routing.