Logo
ScienceStack
Table of Contents
Fetching ...
Sign In

Flexing RISC-V Instruction Subset Processors to Extreme Edge

Alireza Raisiardali, Konstantinos Iordanou, Jedrzej Kufel, Kowshik Gudimetla, Kris Myny, Emre Ozer

TL;DR

The paper tackles the need for ultra-low-cost, flexible electronics in Extreme Edge applications by introducing RISC-V Instruction SubSet Processors (RISSPs) implemented as FlexICs. It presents a methodology that builds RISSPs from a library of pre-verified instruction hardware blocks, assembling domain-specific single-cycle cores by stitching together ModularEX with fixed fetch/register/memory interfaces, while integrating verification at all stages. A Generative AI–assisted retargeting flow enables updating RISSPs for long-lasting edges without creating a new toolchain, by rewriting unsupported instructions as macros within the supported subset. Experimental results show RISSPs reduce area and power versus full ISA implementations, and significantly outperform a baseline 32-bit Serv core in energy efficiency, with physical FlexIC implementations achieving notable area and power savings. Together, the approach supports rapid generation and deployment of domain-specific, energy-efficient processors for extreme edge scenarios.

Abstract

This paper presents an automated approach for designing processors that support a subset of the RISC-V instruction set architecture (ISA) for a new class of applications at Extreme Edge. The electronics used in extreme edge applications must be area and power-efficient, but also provide additional qualities, such as low cost, conformability, comfort and sustainability. Flexible electronics, rather than silicon-based electronics, will be able to meet the above qualities. For this purpose, we propose a methodology for generating RISC-V instruction subset processors (RISSPs) tailored to these applications and implementing them as flexible integrated circuits (FlexICs). The methodology makes verification an integral part of the processor design by treating each instruction in the ISA as a discrete, fully functional, pre-verified hardware block. It automatically builds a custom processor by stitching together the instruction hardware blocks required by an application or a set of applications in a specific domain. We generate RISSPs using the proposed methodology for three extreme edge applications, and embedded applications from the Embench benchmark suite. When synthesized, RISSPs can achieve 8-to-43% reduction in area and 3-to-30% reduction in power compared to a processor supporting the full RISC-V ISA, and are also on average ~40 times more energy efficient than Serv - the world's smallest 32-bit RISC-V processor. When physically implemented as FlexICs, the three extreme edge RISSPs achieve up to 42% area and 21% power savings with respect to the full RISC-V processor.

Flexing RISC-V Instruction Subset Processors to Extreme Edge

TL;DR

The paper tackles the need for ultra-low-cost, flexible electronics in Extreme Edge applications by introducing RISC-V Instruction SubSet Processors (RISSPs) implemented as FlexICs. It presents a methodology that builds RISSPs from a library of pre-verified instruction hardware blocks, assembling domain-specific single-cycle cores by stitching together ModularEX with fixed fetch/register/memory interfaces, while integrating verification at all stages. A Generative AI–assisted retargeting flow enables updating RISSPs for long-lasting edges without creating a new toolchain, by rewriting unsupported instructions as macros within the supported subset. Experimental results show RISSPs reduce area and power versus full ISA implementations, and significantly outperform a baseline 32-bit Serv core in energy efficiency, with physical FlexIC implementations achieving notable area and power savings. Together, the approach supports rapid generation and deployment of domain-specific, energy-efficient processors for extreme edge scenarios.

Abstract

This paper presents an automated approach for designing processors that support a subset of the RISC-V instruction set architecture (ISA) for a new class of applications at Extreme Edge. The electronics used in extreme edge applications must be area and power-efficient, but also provide additional qualities, such as low cost, conformability, comfort and sustainability. Flexible electronics, rather than silicon-based electronics, will be able to meet the above qualities. For this purpose, we propose a methodology for generating RISC-V instruction subset processors (RISSPs) tailored to these applications and implementing them as flexible integrated circuits (FlexICs). The methodology makes verification an integral part of the processor design by treating each instruction in the ISA as a discrete, fully functional, pre-verified hardware block. It automatically builds a custom processor by stitching together the instruction hardware blocks required by an application or a set of applications in a specific domain. We generate RISSPs using the proposed methodology for three extreme edge applications, and embedded applications from the Embench benchmark suite. When synthesized, RISSPs can achieve 8-to-43% reduction in area and 3-to-30% reduction in power compared to a processor supporting the full RISC-V ISA, and are also on average ~40 times more energy efficient than Serv - the world's smallest 32-bit RISC-V processor. When physically implemented as FlexICs, the three extreme edge RISSPs achieve up to 42% area and 21% power savings with respect to the full RISC-V processor.
Paper Structure (20 sections, 12 figures, 3 tables)

This paper contains 20 sections, 12 figures, 3 tables.

Table of Contents

  1. Introduction
  2. Related Work
  3. Methodology of RISSP Generation
  4. Concept of Instruction Hardware Blocks
  5. Modular Execution Unit
  6. RISSP Construction
  7. Verification
  8. Development of the Pre-verified Full ISA Hardware Library
  9. Integration-level Verification
  10. Experimental Evaluation
  11. Instruction Subset Profile of Applications
  12. FlexIC Synthesis Results
  13. Maximum Frequency Analysis
  14. Area Analysis
  15. Power Analysis
  16. ...and 5 more sections

Figures (12)

  • Figure 1: FlexIC technology. (a) A 200 mm wafer on a polyimide substrate, (b) A FlexIC is an integrated circuit manufactured on a polyimide wafer substrate. The semiconductor material is metal-oxide called Indium-Gallium-Zinc-Oxide (IGZO) that can be manufactured at low temperatures. The image of the FlexIC diced from the polyimide wafer is shown. It is an ultra-thin (30 µ m) and physically flexible or bendable.
  • Figure 2: RISSP generation methodology. STEP 0: Development of the pre-verified full ISA hardware library, which is the one-time development effort of the methodology; STEP 1: Generation of domain-specific instruction subset from an application or a set of applications from a domain; STEP 2: Pulling instruction hardware blocks for the domain-specific instruction set from the pre-verified full ISA hardware library, and formation of ModularEX; STEP 3: Construction of the RISSP by stitching ModularEX with fixed units like memory interfaces and the register file
  • Figure 3: A single-cycle RISSP microarchitecture created by stitching together ModularEX, the fixed units (i.e., Fetch and RF) and Memory Interfaces
  • Figure 4: The development of the pre-verified full ISA hardware library
  • Figure 5: Results of instruction profiling and characterization of the three extreme edge applications, and the benchmarks in Embench using different compiler optimization flags. The top diagram presents the codesize in KBytes and the bottom diagram illustrates the number of distinct instructions from the RV32E ISA across different optimization flags.
  • ...and 7 more figures