Scalable 49-Channel Neural Recorder with an Event-Driven Ramp ADC and PCA Compression in 28 nm CMOS

TL;DR

This work tackles the data-rate and power bottlenecks of high-density neural recording for implantable devices by introducing a 49-channel ASIC that integrates an event-driven ramp ADC with on-chip PCA-based spike compression. The ramp ADC digitizes only spike-related samples using a dual-threshold, shared-ramp scheme, while the compression module reduces data by up to $328$× through PCA applied to concatenated spike waveforms, preserving essential spike-sortable information. The system achieves a measured total power of $534$ μW and occupies a compact footprint of $1.4\times1.4$ mm, enabling scalable wireless neural interfaces with dense electrode arrays. Although compression slightly degrades spike-sorting accuracy (e.g., from $79.5\%$ to $74.9\%$ on synthetic data), the approach significantly reduces data bandwidth and energy per channel, paving the way for large-scale, implantable neural interfaces with practical transmission budgets.

Abstract

Neural interfaces advance neuroscience research and therapeutic innovations by accurately measuring neuronal activity. However, recording raw data from numerous neurons results in substantial amount of data and poses challenges for wireless transmission. While conventional neural recorders consume energy to digitize and process the full neural signal, only a fraction of this data carries essential spiking information. Leveraging on this signal sparsity, this paper introduces a neural recording integrated circuit in TSMC 28nm CMOS. It features an event-driven ramp analog-to-digital converter, and a spike compression module based on principal component analysis. The circuit consists of 49 channels, each occupying an on-chip area of 50 $\times$ 60 $μ$m$^2$. The circuit measures 1370 $\times$ 1370 $μ$m$^2$ and consumes 534 $μ$W. Compression testing on a synthetic dataset demonstrated an 8.8-fold reduction compared to raw spikes and a 328-fold reduction relative to the raw signal. This compression approach maintained a spike sorting accuracy of 74.9%, compared to the 79.5% accuracy obtained with the raw signal. The paper details the architecture and performance outcomes of the neural recording circuit and its compression module.

Figures (13)

• Figure 1: Proposed event-driven digitization and compression scheme: A ramp analog-to-digital converter begins digitizing upon crossing a primary threshold (red dots) to identify potential spike waveform onsets. If a secondary threshold is crossed within N samples, the system proceeds to capture the entire spike duration (green dots); otherwise, it resets. Following spike detection, a spike compression module applies the principal component analysis.
• Figure 2: Block diagram of the ASIC. Each of the 49 pixels includes a front-end circuit (A.) comprising a DC-coupled LNA, a sample-and-hold circuit and a comparator. A ramp analog-to-digital converter (B.) generates a sawtooth waveform distributed to every pixel in the array. When the ramp crosses the amplified electrode signal, the comparator triggers. The readout circuit detects that transition, and outputs the digitized value and the electrode address to a spike detection and compression circuit (C.). A central controller (D.) manages the communication and configuration through a register bank.
• Figure 3: DC-coupled low-noise amplifier (LNA) architecture. The input electrode signal (Vin) is fed to Amp1. Amp2 provides DC offset rejection by implementing a low-pass filter formed by the pseudo-resistor $R_{fb}$ and capacitor $C_{fb}$ in the feedback path of Amp1. A comparator (Cmp), coupled with a ramp generator, digitizes the signal buffered by the sample and hold circuit. The circuit uses a Cfb capacitor of 1 pF and a sample and hold capacitor of 235 fF.
• Figure 4: Ramp generator circuit based on a unary-weighted split-capacitor array. An 8-bit counter is converted by a thermometer decoder to a 256-bit code and fed to a unary-weighted split-capacitor array.
• Figure 5: Event-driven digitization scheme: A first event below thresholds is not digitized. A second event, above thresholds, is digitized and triggers the pixel. A third event below threshold is digitized due to the triggered pixel. Lastly, the spike detector circuit clears the trigger after a configurable time window (clear trigger signal).