In-Situ Hardware Error Detection Using Specification-Derived Petri Net Models and Behavior-Derived State Sequences

TL;DR

The paper tackles soft errors that threaten control-flow in hardware accelerators by introducing two in-situ detectors: Petri nets derived from design specifications and state sequences derived from runtime behavior. It provides a concrete workflow for constructing, evaluating, and implementing these detectors, and validates them on four diverse designs (CNN convolution, Gaussian blur, AES, and an NoC router). Across fault-injection campaigns, both approaches achieve high detection rates with only a few to about 10 percent area overhead, outperforming naive register duplication for upstream-input faults. The work demonstrates that practitioners can selectively apply and combine these methods to meet diverse reliability and area constraints, enabling practical, robust, in-situ error detection in safety-critical hardware accelerators.

Abstract

In hardware accelerators used in data centers and safety-critical applications, soft errors and resultant silent data corruption significantly compromise reliability, particularly when upsets occur in control-flow operations, leading to severe failures. To address this, we introduce two methods for monitoring control flows: using specification-derived Petri nets and using behavior-derived state transitions. We validated our method across four designs: convolutional layer operation, Gaussian blur, AES encryption, and a router in Network-on-Chip. Our fault injection campaign targeting the control registers and primary control inputs demonstrated high error detection rates in both datapath and control logic. Synthesis results show that a maximum detection rate is achieved with a few to around 10% area overhead in most cases. The proposed detectors quickly detect 48% to 100% of failures resulting from upsets in internal control registers and perturbations in primary control inputs. The two proposed methods were compared in terms of area overhead and error detection rate. By selectively applying these two methods, a wide range of area constraints can be accommodated, enabling practical implementation and effectively enhancing error detection capabilities.

Figures (17)

• Figure 1: Proposed method from generating Petri nets to implementing those as detectors.
• Figure 2: Simple Petri net.
• Figure 3: Architecture of Petri-net-based error detector.
• Figure 4: Proposed error detection method using state sequences.
• Figure 5: Monitored signals at different hierarchical levels.