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CVA6S+: A Superscalar RISC-V Core with High-Throughput Memory Architecture

Riccardo Tedeschi, Gianmarco Ottavi, Côme Allart, Nils Wistoff, Zexin Fu, Filippo Grillotti, Fabio De Ambroggi, Elio Guidetti, Jean-Baptiste Rigaud, Olivier Potin, Jean Roch Coulon, César Fuguet, Luca Benini, Davide Rossi

TL;DR

CVA6S+ tackles IPC bottlenecks in scalar RISC-V cores by building on CVA6S to create a dual-issue design enriched with register renaming, a two-level private-history branch predictor, ALU-to-ALU operand forwarding, and integrated FPU. Coupled with the HPDCache non-blocking data path, the design achieves $43.5\%$ IPC improvement over the scalar CVA6 and $10.9\%$ over CVA6S, while incurring under $9.3\%$ area overhead; memory bandwidth improves by $74.1\%$ with HPDCache. The evaluation on a FPGA-based Cheshire/Genesys 2 platform uses RV32IMAC with a, b, c, s bitmanip extensions to demonstrate practical gains in embedded workloads (Embench-IoT) and memory-intensive patterns (RaiderSTREAM). The work demonstrates the viability of combining microarchitectural enhancements with a non-blocking cache to deliver high-throughput, memory-bandwidth-efficient RISC-V cores for automotive and embedded domains.

Abstract

Open-source RISC-V cores are increasingly adopted in high-end embedded domains such as automotive, where maximizing instructions per cycle (IPC) is becoming critical. Building on the industry-supported open-source CVA6 core and its superscalar variant, CVA6S, we introduce CVA6S+, an enhanced version incorporating improved branch prediction, register renaming and enhanced operand forwarding. These optimizations enable CVA6S+ to achieve a 43.5% performance improvement over the scalar configuration and 10.9% over CVA6S, with an area overhead of just 9.30% over the scalar core (CVA6). Furthermore, we integrate CVA6S+ with the OpenHW Core-V High-Performance L1 Dcache (HPDCache) and report a 74.1% bandwidth improvement over the legacy CVA6 cache subsystem.

CVA6S+: A Superscalar RISC-V Core with High-Throughput Memory Architecture

TL;DR

CVA6S+ tackles IPC bottlenecks in scalar RISC-V cores by building on CVA6S to create a dual-issue design enriched with register renaming, a two-level private-history branch predictor, ALU-to-ALU operand forwarding, and integrated FPU. Coupled with the HPDCache non-blocking data path, the design achieves IPC improvement over the scalar CVA6 and over CVA6S, while incurring under area overhead; memory bandwidth improves by with HPDCache. The evaluation on a FPGA-based Cheshire/Genesys 2 platform uses RV32IMAC with a, b, c, s bitmanip extensions to demonstrate practical gains in embedded workloads (Embench-IoT) and memory-intensive patterns (RaiderSTREAM). The work demonstrates the viability of combining microarchitectural enhancements with a non-blocking cache to deliver high-throughput, memory-bandwidth-efficient RISC-V cores for automotive and embedded domains.

Abstract

Open-source RISC-V cores are increasingly adopted in high-end embedded domains such as automotive, where maximizing instructions per cycle (IPC) is becoming critical. Building on the industry-supported open-source CVA6 core and its superscalar variant, CVA6S, we introduce CVA6S+, an enhanced version incorporating improved branch prediction, register renaming and enhanced operand forwarding. These optimizations enable CVA6S+ to achieve a 43.5% performance improvement over the scalar configuration and 10.9% over CVA6S, with an area overhead of just 9.30% over the scalar core (CVA6). Furthermore, we integrate CVA6S+ with the OpenHW Core-V High-Performance L1 Dcache (HPDCache) and report a 74.1% bandwidth improvement over the legacy CVA6 cache subsystem.
Paper Structure (4 sections, 1 figure, 1 table)

This paper contains 4 sections, 1 figure, 1 table.

Table of Contents

  1. Introduction
  2. Implementation
  3. Evaluation
  4. Conclusion

Figures (1)

  • Figure 1: Performance assessment of the different CVA6 versions and cache subsystems. (a) compares IPC improvements on the integer kernels of the Embench IoT suite, (b) the bandwidth gain from adopting the HPDCache.