Logo
ScienceStack
Table of Contents
Fetching ...
Sign In

AI-Powered Agile Analog Circuit Design and Optimization

Jinhai Hu, Wang Ling Goh, Yuan Gao

TL;DR

This work tackles the optimization challenge in analog circuit design by integrating AI into both device‑level sizing and system‑level co‑design. It introduces a MOBO framework with a GP surrogate and qEHVI acquisition to directly optimize transistor parameters of a linearly tunable transconductor, achieving a 24% IRN reduction and a 102% gain in $G_m$ range over 35 SPICE trials. It also demonstrates system‑level co‑design by embedding the analog bandpass filter transfer function into the KWS training loop, using trainable scalars $\phi_g$ and $\phi_C$ and a joint loss $L_{BPF}$ to balance accuracy with power and area; results on Google Speech Commands validate improvements. Together, the findings illustrate AI's potential to accelerate analog design iterations and enable joint optimization of hardware with application‑level performance.

Abstract

Artificial intelligence (AI) techniques are transforming analog circuit design by automating device-level tuning and enabling system-level co-optimization. This paper integrates two approaches: (1) AI-assisted transistor sizing using Multi-Objective Bayesian Optimization (MOBO) for direct circuit parameter optimization, demonstrated on a linearly tunable transconductor; and (2) AI-integrated circuit transfer function modeling for system-level optimization in a keyword spotting (KWS) application, demonstrated by optimizing an analog bandpass filter within a machine learning training loop. The combined insights highlight how AI can improve analog performance, reduce design iteration effort, and jointly optimize analog components and application-level metrics.

AI-Powered Agile Analog Circuit Design and Optimization

TL;DR

This work tackles the optimization challenge in analog circuit design by integrating AI into both device‑level sizing and system‑level co‑design. It introduces a MOBO framework with a GP surrogate and qEHVI acquisition to directly optimize transistor parameters of a linearly tunable transconductor, achieving a 24% IRN reduction and a 102% gain in range over 35 SPICE trials. It also demonstrates system‑level co‑design by embedding the analog bandpass filter transfer function into the KWS training loop, using trainable scalars and and a joint loss to balance accuracy with power and area; results on Google Speech Commands validate improvements. Together, the findings illustrate AI's potential to accelerate analog design iterations and enable joint optimization of hardware with application‑level performance.

Abstract

Artificial intelligence (AI) techniques are transforming analog circuit design by automating device-level tuning and enabling system-level co-optimization. This paper integrates two approaches: (1) AI-assisted transistor sizing using Multi-Objective Bayesian Optimization (MOBO) for direct circuit parameter optimization, demonstrated on a linearly tunable transconductor; and (2) AI-integrated circuit transfer function modeling for system-level optimization in a keyword spotting (KWS) application, demonstrated by optimizing an analog bandpass filter within a machine learning training loop. The combined insights highlight how AI can improve analog performance, reduce design iteration effort, and jointly optimize analog components and application-level metrics.
Paper Structure (4 sections, 4 equations, 5 figures)

This paper contains 4 sections, 4 equations, 5 figures.

Table of Contents

  1. Introduction
  2. AI for Circuit Schematic Design
  3. AI for System-Level Optimization
  4. Conclusion

Figures (5)

  • Figure 1: Proposed analog circuit optimization framework using MOBO.
  • Figure 2: MOBO process on (left) tunable parameters and (right) performance metrics through 35 trials.
  • Figure 3: The block diagram of the proposed learnable audio AFE and the schematic of the analog filters.
  • Figure 4: Frequency response of (a)(c) initial and (b)(d) learned BPFs at different Q-factor initialization.
  • Figure 5: (a) Performance through SNR-aware training. (b) Hardware utilization through co-design.