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QiMeng-CPU-v2: Automated Superscalar Processor Design by Learning Data Dependencies

Shuyao Cheng, Rui Zhang, Wenkai He, Pengwei Jin, Chongxiao Li, Zidong Du, Xing Hu, Yifan Hao, Guanglin Xu, Yuanbo Wen, Ling Li, Qi Guo, Yunji Chen

TL;DR

This work tackles the challenge of automatically designing superscalar CPUs by learning inter-instruction data dependencies with a hardware-friendly model, State-BSD, which combines a lightweight state-selector trained by simulated annealing and a high-precision state-speculator trained via BSD expansion. The approach enables on-the-fly prediction of dependent data, partitioned into MEM, PC, and GPR sub-predictors, to achieve parallelism while guaranteeing functional correctness through 100% precision. The authors realize QiMeng-CPU-v2, a RISCV-32IA superscalar CPU that substantially outperforms prior automated designs (about $382\times$ throughput) and rivals human-designed cores like ARM Cortex A53, with FPGA validation on Linux/SPEC and a plan for 28nm tape-out. This work demonstrates a viable path for AI-assisted hardware design of complex ILP architectures by explicitly leveraging internal processor states to learn data dependencies.

Abstract

Automated processor design, which can significantly reduce human efforts and accelerate design cycles, has received considerable attention. While recent advancements have automatically designed single-cycle processors that execute one instruction per cycle, their performance cannot compete with modern superscalar processors that execute multiple instructions per cycle. Previous methods fail on superscalar processor design because they cannot address inter-instruction data dependencies, leading to inefficient sequential instruction execution. This paper proposes a novel approach to automatically designing superscalar processors using a hardware-friendly model called the Stateful Binary Speculation Diagram (State-BSD). We observe that processor parallelism can be enhanced through on-the-fly inter-instruction dependent data predictors, reusing the processor's internal states to learn the data dependency. To meet the challenge of both hardware-resource limitation and design functional correctness, State-BSD consists of two components: 1) a lightweight state-selector trained by the simulated annealing method to detect the most reusable processor states and store them in a small buffer; and 2) a highly precise state-speculator trained by the BSD expansion method to predict the inter-instruction dependent data using the selected states. It is the first work to achieve the automated superscalar processor design, i.e. QiMeng-CPU-v2, which improves the performance by about $380\times$ than the state-of-the-art automated design and is comparable to human-designed superscalar processors such as ARM Cortex A53.

QiMeng-CPU-v2: Automated Superscalar Processor Design by Learning Data Dependencies

TL;DR

This work tackles the challenge of automatically designing superscalar CPUs by learning inter-instruction data dependencies with a hardware-friendly model, State-BSD, which combines a lightweight state-selector trained by simulated annealing and a high-precision state-speculator trained via BSD expansion. The approach enables on-the-fly prediction of dependent data, partitioned into MEM, PC, and GPR sub-predictors, to achieve parallelism while guaranteeing functional correctness through 100% precision. The authors realize QiMeng-CPU-v2, a RISCV-32IA superscalar CPU that substantially outperforms prior automated designs (about throughput) and rivals human-designed cores like ARM Cortex A53, with FPGA validation on Linux/SPEC and a plan for 28nm tape-out. This work demonstrates a viable path for AI-assisted hardware design of complex ILP architectures by explicitly leveraging internal processor states to learn data dependencies.

Abstract

Automated processor design, which can significantly reduce human efforts and accelerate design cycles, has received considerable attention. While recent advancements have automatically designed single-cycle processors that execute one instruction per cycle, their performance cannot compete with modern superscalar processors that execute multiple instructions per cycle. Previous methods fail on superscalar processor design because they cannot address inter-instruction data dependencies, leading to inefficient sequential instruction execution. This paper proposes a novel approach to automatically designing superscalar processors using a hardware-friendly model called the Stateful Binary Speculation Diagram (State-BSD). We observe that processor parallelism can be enhanced through on-the-fly inter-instruction dependent data predictors, reusing the processor's internal states to learn the data dependency. To meet the challenge of both hardware-resource limitation and design functional correctness, State-BSD consists of two components: 1) a lightweight state-selector trained by the simulated annealing method to detect the most reusable processor states and store them in a small buffer; and 2) a highly precise state-speculator trained by the BSD expansion method to predict the inter-instruction dependent data using the selected states. It is the first work to achieve the automated superscalar processor design, i.e. QiMeng-CPU-v2, which improves the performance by about than the state-of-the-art automated design and is comparable to human-designed superscalar processors such as ARM Cortex A53.
Paper Structure (18 sections, 2 equations, 3 figures, 4 tables)

This paper contains 18 sections, 2 equations, 3 figures, 4 tables.

Table of Contents

  1. Introduction
  2. Problem Statement
  3. Superscalar Processor Design
  4. Managing Inter-Instruction Dependencies: Learning a High-precision Predictor
  5. The design correctness of the superscalar processor.
  6. The design performance of the superscalar processor.
  7. Methodology
  8. Design Overview
  9. Train the Data Predictor with State-BSD
  10. The difference between the BSD and State-BSD.
  11. Evaluation
  12. Comparison with the State-of-the-art Automated Design Methods
  13. Comparison with the human design
  14. State-BSD Algorithm Effectiveness Analysis
  15. Related Work
  16. ...and 3 more sections

Figures (3)

  • Figure 1: An example of breaking data dependencies by a predictor in the superscalar processor design.(a) For the program slice (Inst.1 and Inst.2) under Read-after-Write (RAW) dependency, without any predictors, these two instructions have to execute one after another. (b) With the data dependency predictor, the predicted data of register $r1$ can be obtained in advance by Inst.2 so that it is no longer blocked by Inst.1.
  • Figure 2: The design overview. (a) The automated designed superscalar processor. It consists of a predictor automatically designed by State-BSD and $k$ execution units. Every clock cycle, the predictor outputs $m$ indicating how many instructions can be execute in parallel, and $\Psi$ indicating the predicted dependent data. (b) The hardware implement of the dependency predictor, consisting of two components: the state-selector and state-speculator. The state-selector is a multiplexer with small buffer, and the state-speculator is a high-precision combinational module. (c) Train the dependency predictor with State-BSD: The selector is trained by simulated annealing, and the speculator is trained by BSD expansion.
  • Figure 3: CPU performance comparison with the state-of-the-art. We compare the performance of the automated designed CPU designed by our method and the state-of-the-art. The red data points are human-designed commercial CPUs with similar performance. The result shows that our design is comparable to Arm Cortex A53 (2010s CPU), while the state-of-the-art automated design is only comparable to Intel 486 (1990s CPU).

Theorems & Definitions (3)

  • Definition 2.1
  • Definition 2.2
  • Definition 3.1