Hardware vs. Software Implementation of Warp-Level Features in Vortex RISC-V GPU

TL;DR

Addressing the gap in warp-level support for Vortex RISC-V GPUs, this work compares hardware and software paths to implement cooperative groups and warp-level primitives. It introduces minimal hardware ISA extensions (vx_vote, vx_shfl, vx_tile) and an extended software parallel-region transformation to realize these features. Evaluation shows a hardware path delivering a geomean IPC improvement of $2.42×$ over the software baseline, with some kernels reaching up to $4×$ speedups, while incurring about $2\%$ area overhead per core; the software path remains viable in area-constrained scenarios. The results demonstrate a practical hardware-software co-design space for warp-level support on open-source RISC-V GPU stacks and inform future work on reductions and flexible CUDA-thread mapping.

Abstract

RISC-V GPUs present a promising path for supporting GPU applications. Traditionally, GPUs achieve high efficiency through the SPMD (Single Program Multiple Data) programming model. However, modern GPU programming increasingly relies on warp-level features, which diverge from the conventional SPMD paradigm. In this paper, we explore how RISC-V GPUs can support these warp-level features both through hardware implementation and via software-only approaches. Our evaluation shows that a hardware implementation achieves up to 4 times geomean IPC speedup in microbenchmarks, while software-based solutions provide a viable alternative for area-constrained scenarios.

Figures (6)

• Figure 1: Vortex GPU and software stack
• Figure 2: Vortex core architecture. Modified sections (highlighted in yellow) support cooperative groups and warp-level functions
• Figure 3: CUDA kernel example and converted Pseudo-code kernel example using hardware intrinsics
• Figure 4: Transformed kernel after applying PR transformation in \ref{['fig:original_code']} ( SW solution)
• Figure 5: Instruction per Cycle(IPC) of 4 different benchmarks