NeuroSim V1.5: Improved Software Backbone for Benchmarking Compute-in-Memory Accelerators with Device and Circuit-level Non-idealities

TL;DR

NeuroSim V1.5 addresses the energy inefficiency of von Neumann architectures by providing a high-fidelity, open-source framework for characterize-and-optimize compute-in-memory (CIM) accelerators. It integrates TensorRT post-training quantization to map pre-trained networks (including transformers) onto CIM, and employs flexible, pre-characterized noise models to capture device- and circuit-level non-idealities across diverse technologies such as nvCap. The framework combines a GPU-accelerated behavioral simulator with a detailed hardware estimator, delivering up to 6.5× runtime improvements over the prior version while enabling systematic design space exploration across accuracy and power, performance, and area. Through extensive case studies, NeuroSim V1.5 demonstrates actionable design insights about array sizing, ADC precision, memory cell granularity, and noise resilience, and it validates its noise-modeling approach against SPICE and silicon data, thus bridging high-fidelity device/circuit modeling with scalable system-level CIM analysis.

Abstract

The exponential growth of artificial intelligence (AI) applications has exposed the inefficiency of conventional von Neumann architectures, where frequent data transfers between compute units and memory create significant energy and latency bottlenecks. Analog Computing-in-Memory (ACIM) addresses this challenge by performing multiply-accumulate (MAC) operations directly in the memory arrays, substantially reducing data movement. However, designing robust ACIM accelerators requires accurate modeling of device- and circuit-level non-idealities. In this work, we present NeuroSim V1.5, introducing several key advances: (1) seamless integration with TensorRT's post-training quantization flow enabling support for more neural networks including transformers, (2) a flexible noise injection methodology built on pre-characterized statistical models, making it straightforward to incorporate data from SPICE simulations or silicon measurements, (3) expanded device support including emerging non-volatile capacitive memories, and (4) up to 6.5x faster runtime than NeuroSim V1.4 through optimized behavioral simulation. The combination of these capabilities uniquely enables systematic design space exploration across both accuracy and hardware efficiency metrics. Through multiple case studies, we demonstrate optimization of critical design parameters while maintaining network accuracy. By bridging high-fidelity noise modeling with efficient simulation, NeuroSim V1.5 advances the design and validation of next-generation ACIM accelerators. All NeuroSim versions are available open-source at https://github.com/neurosim/NeuroSim.

Figures (9)

• Figure 1: Overview of NeuroSim V1.5: This update revamped the software backbone to support arbitrary neural network models and provide a more intuitive noise simulation workflow tailored to device and circuit experts. NeuroSim V1.5 enables users to evaluate inference accuracy across diverse architectures, including custom convolutional neural networks and transformers, while simulating various device types and noise sources. The platform uniquely supports power, performance, and area (PPA) estimations, facilitating comprehensive system-level design space exploration. Key new features include optimized noise modeling, compatibility with advanced non-volatile memory technologies, and improved runtime performance.
• Figure 2: Procedure for ACIM behavioral simulation in NeuroSim V1.5. (1) Inputs and weights are quantized from floating point to integer. (2) Inputs and weights unfolded and (3) mapped to compute-in-memory arrays. (4) Analog MACs are calculated with analytical circuit models. (5) Noise is injected either to memory devices or to digital MAC outputs. (6) ADC outputs are shifted and added. (7) Outputs from memory arrays are accumulated and concatenated. (8) Accumulated outputs are folded into output tensors. (9) Outputs are de-quantized from integer back to floating-point.
• Figure 3: NeuroSim V1.5 flowchart. Device expert mode: user provides device data (memory state variation, stuck-at-faults, state drift). Circuit expert mode: user provides statistical data on MAC outputs from SPICE Monte-Carlo simulations or tapeout measurements.
• Figure 4: Example design space exploration for 22nm RRAM. Each point represents a unique configuration. Bit-serial input was used for every design. Designs with highest TOPS/W use array sizes of $32\times 32$ and $64\times 64$.
• Figure 5: Inference accuracy of VGG8 on CIFAR-10, ResNet18 on CIFAR-100, and ResNet50 on ImageNet using V1.5 across different RRAM (single-level cell) variations.