Efficient FPGA Implementation of Time-Domain Popcount for Low-Complexity Machine Learning

TL;DR

This work targets bottlenecks in low-complexity ML, notably popcount and argmax, within Tsetlin Machines (TMs). It introduces a time-domain popcount implemented with Programmable Delay Lines (PDLs) and arbiters, designed for asynchronous FPGA architectures and accompanied by a practical design flow to mitigate delay skew. The proposed approach maintains lossless accuracy while delivering up to 38% lower inference latency, up to 43.1% lower dynamic power, and up to 15% fewer resources compared to adder-based popcount in TM inference, demonstrated on Iris and MNIST with a Xilinx Zynq FPGA. The method offers scalable advantages for multi-class TM tasks and suggests broader applicability to BNNs, with future work aimed at asynchronous pipelining for deeper networks. The work emphasizes the importance of monotonic Hamming-weight–to–delay relationships and symmetry-aware hardware design for reliable time-domain computation.

Abstract

Population count (popcount) is a crucial operation for many low-complexity machine learning (ML) algorithms, including Tsetlin Machine (TM)-a promising new ML method, particularly well-suited for solving classification tasks. The inference mechanism in TM consists of propositional logic-based structures within each class, followed by a majority voting scheme, which makes the classification decision. In TM, the voters are the outputs of Boolean clauses. The voting mechanism comprises two operations: popcount for each class and determining the class with the maximum vote by means of an argmax operation. While TMs offer a lightweight ML alternative, their performance is often limited by the high computational cost of popcount and comparison required to produce the argmax result. In this paper, we propose an innovative approach to accelerate and optimize these operations by performing them in the time domain. Our time-domain implementation uses programmable delay lines (PDLs) and arbiters to efficiently manage these tasks through delay-based mechanisms. We also present an FPGA design flow for practical implementation of the time-domain popcount, addressing delay skew and ensuring that the behavior matches that of the model's intended functionality. By leveraging the natural compatibility of the proposed popcount with asynchronous architectures, we demonstrate significant improvements in an asynchronous TM, including up to 38% reduction in latency, 43.1% reduction in dynamic power, and 15% savings in resource utilization, compared to synchronous TMs using adder-based popcount.

Figures (12)

• Figure 1: (a) TMs, where each TM is assigned to a certain class and each clause has been trained to recognize a pattern of Boolean inputs, represented by propositional logic. Popcount counts the number of clauses supporting (+1) and opposing (-1) each class, with the classification determined by the class with the highest popcount, using argmax. (b) A BNN neuron. $x_0$ and $x_1$ are input features or activation values.
• Figure 2: Time-domain popcount and comparison, implemented by PDL and arbiter, respectively.
• Figure 3: Implementation flow for time-domain popcount with example Xilinx Tcl scripts.
• Figure 4: PDL placement on Xilinx FPGA, where each CLB consists of two slices, and each slice contains four LUTs. Each PDL is mapped to CLBs positioned identically relative to their neighboring switchboxes. Delay elements are consistently placed in the same relative position, specifically within a designated LUT in a particular slice of each CLB.
• Figure 5: Symmetric PDL and delay element layout.