ForgeEDA: A Comprehensive Multimodal Dataset for Advancing EDA

TL;DR

ForgeEDA addresses the data scarcity in EDA by providing a large, multimodal dataset spanning RTL code, PM nets, placed nets, and AIGs from 1,189 real-world designs. It enables benchmarking across logic synthesis, AIG optimization, and AI4EDA tasks, and includes 83,155 sub-AIGs and 4,450 PM/placed nets with graph representations for PyTorch Geometric. Experiments show commercial DCU outperforms open-source Yosys, and AI models trained on ForgeEDA, especially PolarGate, outperform generic GNNs on probability prediction and equivalent gate tasks. The dataset supports end-to-end evaluation across design stages and improves AI4EDA performance with large-scale training data, accelerating open-source EDA progress.

Abstract

We introduce ForgeEDA, an open-source comprehensive circuit dataset across various categories. ForgeEDA includes diverse circuit representations such as Register Transfer Level (RTL) code, Post-mapping (PM) netlists, And-Inverter Graphs (AIGs), and placed netlists, enabling comprehensive analysis and development. We demonstrate ForgeEDA's utility by benchmarking state-of-the-art EDA algorithms on critical tasks such as Power, Performance, and Area (PPA) optimization, highlighting its ability to expose performance gaps and drive advancements. Additionally, ForgeEDA's scale and diversity facilitate the training of AI models for EDA tasks, demonstrating its potential to improve model performance and generalization. By addressing limitations in existing datasets, ForgeEDA aims to catalyze breakthroughs in modern IC design and support the next generation of innovations in EDA.

Figures (3)

• Figure 1: Overview of ForgeEDA
• Figure 2: AIG Optimization Results
• Figure 3: AIG Technology Mapping Results