Dendritic Computing with Multi-Gate Ferroelectric Field-Effect Transistors

TL;DR

The paper tackles the inefficiency of point-neuron models by introducing a multi-gate ferroelectric FeFET that implements dendritic processing through ferroelectric nonlinearity, with somatic output arising from channel conduction. It combines experimental fabrication and electrical characterization with a calibrated, device-level model and a device-circuit-algorithm co-simulation framework to evaluate dendritic computation in crossbar-based neuromorphic hardware. Key contributions include (i) experimental validation of a 3-gate FeFET, (ii) a calibrated model linking ferroelectric domain switching to floating-gate dynamics, and (iii) a co-design framework showing dendritic networks achieve comparable or better Fashion-MNIST accuracy with ~17× fewer trainable parameters, highlighting substantial hardware efficiency for edge AI. The work demonstrates that ferroelectric dendritic hardware can markedly reduce resource needs while enhancing learning capacity, offering a promising path toward energy-efficient, scalable neuromorphic systems.

Abstract

Although inspired by neuronal systems in the brain, artificial neural networks generally employ point-neurons, which offer far less computational complexity than their biological counterparts. Neurons have dendritic arbors that connect to different sets of synapses and offer local non-linear accumulation - playing a pivotal role in processing and learning. Inspired by this, we propose a novel neuron design based on a multi-gate ferroelectric field-effect transistor that mimics dendrites. It leverages ferroelectric nonlinearity for local computations within dendritic branches, while utilizing the transistor action to generate the final neuronal output. The branched architecture paves the way for utilizing smaller crossbar arrays in hardware integration, leading to greater efficiency. Using an experimentally calibrated device-circuit-algorithm co-simulation framework, we demonstrate that networks incorporating our dendritic neurons achieve superior performance in comparison to much larger networks without dendrites ($\sim$17$\times$ fewer trainable weight parameters). These findings suggest that dendritic hardware can significantly improve computational efficiency, and learning capacity of neuromorphic systems optimized for edge applications.

Figures (15)

• Figure 1: Overview of Dendritic Computing with Multi-gate FeFET. (a) Signal from one neuron's axon terminals travel to the next neuron's dendrites through the synaptic cleft. It reaches the neuron's cell body or soma and is then propagated forward. (b) An n-gate FeFET structure along with the Transmission Electron Microscopy (TEM) cross-sectional images of the material stack. (c) The dendritic nonlinearity is mapped to the partial polarization switching of the ferroelectric layer, while the somatic accumulation occurs through charge accretion at the shared floating gate. The somatic nonlinearity is mapped to the FET switching characteristics. (d) The scalability and back-end-of-line compatibility of the ferroelectric layers enables us to integrate the multi-gate FeFET device vertically in 3D architectures to ensure high density. The devices are interfaced with ground select transistors/line (GSL) and string select transistors/line (SSL) for proper operation. (e) The multi-gate device symbol. Its structure can be abstracted as multiple ferroelectric capacitors connected in parallel with a FET in series connection below. The partial polarization switching characteristics induces a non-linear component to the floating gate voltage ($\phi_F$), which then modifies the channel characteristics to obtain the modulated drain current, the final neuronal output.
• Figure 2: Characterization of Neuronal Behavior of the Multi-gate FeFET. (a) Experimental setup for measuring the multi-gate FeFET characteristics (3-gates). (b) Each gate receives a reset pulse followed by a set/programming pulse, during which the drain current is measured for an applied drain voltage, $V_{DS}$. (c-k) Drain current $I_D$ with respect to applied set voltage to the first gate, $V_1$. For each panel, the different colored curves represent different set pulse values applied to the second gate, $V_2$. Likewise, the set voltage applied to the third terminal, $V_3$ remains constant for each panel and is noted at the bottom right of the panel. It should be noted that the gates are interchangeable, and the same results can be obtained by selecting any other relative combination. The calibrated model (solid lines) matches well with the experimental data (represented with $\times$’s).
• Figure 3: Impact of Ferroelectric Non-linear Switching. Drain current, $I_D$ as one of the gate voltages ($V_1$) is swept from $0V$ to $4V$ for different amplitudes of $V_2$ and $V_3$ for our multi-gate dendritic device. Solid and dashed lines represent simulated and experimental results respectively. (a) $V_2=2V, V_3=0V$; $V_2=1V, V_3=1V$ and $V_2=0V, V_3=2V$, (b) $V_2=3V, V_3=0V$; $V_2=2V, V_3=1V$; $V_2=1V, V_3=2V$ and $V_2=0V, V_3=3V$, (c) $V_2=4V, V_3=0V$; $V_2=3V, V_3=1V$; $V_2=2V, V_3=2V$; $V_2=1V, V_3=3V$ and $V_2=0V, V_3=4V$. Due to the nonlinear interactions, the $I_D$ curves vary for the different cases. Note, all the gates are interchangeable. (d) Drain current, $I_D$ vs. gate voltage $V_1$ with purely capacitive dendritic gates for the input voltage cases shown in (a) – (c). The inputs overlap as there is no non-linear component in the accumulation.
• Figure 4: Network-level Performance evaluation. (a) The proposed deep dendritic neural network architecture with $k=3$ dendritic branches. In each dendritic layer, each branch is connected to a subset of the previous layer. We have color-coded the input layer to show how they are connected to different branches. These dendritic layers can be stacked to create deep architectures. (b) The circuit architecture of the proposed dendritic layer. Each color, like (a), denotes a separate crossbar array that is interfaced with different gates of our device. For applied drain voltage, $V_{DS}$, the resultant drain currents are the outputs for the next layer. This architecture allows us to optimize our device based on the crossbar array size. Additional current-to-voltage converters, not shown for sake of simplicity, will be needed to interface the gates to the crossbar columns. (c) The Fashion-MNIST dataset, consisting of grayscale images assorted into 10 categories, was used for training and evaluating the network-level performance of networks with and without dendrites. (d) Test accuracy of networks with and without dendrites. Dendritic functionality is enabled by the multi-gate FeFET. We find that the network with dendrites is able to achieve equivalent performance to much larger (in terms of trainable weight parameters) networks without dendrites. (e) Performance improvements ($\Delta Accuracy$) on the test set, with respect to a network with equal trainable weight parameters but no dendrites. It is revealed that the efficacy of the dendrites increases as the total number of parameters decreases.
• Figure S1: Polarization switching observed for the ferroelectric capacitors in the gate stack. (a) Input voltage to the capacitor is a triangular wave with an amplitude of $2.5V$ and time period of $40\mu s$. (b) Charge vs voltage characteristics of the ferroelectric capacitor. The hysteresis indicates the ferroelectric polarization switching.