Logo
ScienceStack
Table of Contents
Fetching ...
Sign In

CIMFlow: An Integrated Framework for Systematic Design and Evaluation of Digital CIM Architectures

Yingjie Qi, Jianlei Yang, Yiou Wang, Yikun Wang, Dayu Wang, Ling Tang, Cenlin Duan, Xiaolin He, Weisheng Zhao

TL;DR

CIMFlow addresses the lack of an integrated design-and-evaluation toolchain for digital CIM by introducing a modular framework with a hierarchical ISA, a two-stage compiler flow (CG-level DP-based partitioning and OP-level MLIR-based mapping), and a cycle-accurate Simulator. It enables end-to-end prototyping from ONNX models to performance metrics, accounting for SRAM capacity constraints through partitioning and dataflow strategies. Experimental results show up to 2.8x speedups and 61.7% energy reductions over baselines, with insights into MG size and NoC bandwidth tradeoffs across DNN models. The framework advances practical digital CIM by supporting design-space exploration and co-design of software and hardware under memory constraints.

Abstract

Digital Compute-in-Memory (CIM) architectures have shown great promise in Deep Neural Network (DNN) acceleration by effectively addressing the "memory wall" bottleneck. However, the development and optimization of digital CIM accelerators are hindered by the lack of comprehensive tools that encompass both software and hardware design spaces. Moreover, existing design and evaluation frameworks often lack support for the capacity constraints inherent in digital CIM architectures. In this paper, we present CIMFlow, an integrated framework that provides an out-of-the-box workflow for implementing and evaluating DNN workloads on digital CIM architectures. CIMFlow bridges the compilation and simulation infrastructures with a flexible instruction set architecture (ISA) design, and addresses the constraints of digital CIM through advanced partitioning and parallelism strategies in the compilation flow. Our evaluation demonstrates that CIMFlow enables systematic prototyping and optimization of digital CIM architectures across diverse configurations, providing researchers and designers with an accessible platform for extensive design space exploration.

CIMFlow: An Integrated Framework for Systematic Design and Evaluation of Digital CIM Architectures

TL;DR

CIMFlow addresses the lack of an integrated design-and-evaluation toolchain for digital CIM by introducing a modular framework with a hierarchical ISA, a two-stage compiler flow (CG-level DP-based partitioning and OP-level MLIR-based mapping), and a cycle-accurate Simulator. It enables end-to-end prototyping from ONNX models to performance metrics, accounting for SRAM capacity constraints through partitioning and dataflow strategies. Experimental results show up to 2.8x speedups and 61.7% energy reductions over baselines, with insights into MG size and NoC bandwidth tradeoffs across DNN models. The framework advances practical digital CIM by supporting design-space exploration and co-design of software and hardware under memory constraints.

Abstract

Digital Compute-in-Memory (CIM) architectures have shown great promise in Deep Neural Network (DNN) acceleration by effectively addressing the "memory wall" bottleneck. However, the development and optimization of digital CIM accelerators are hindered by the lack of comprehensive tools that encompass both software and hardware design spaces. Moreover, existing design and evaluation frameworks often lack support for the capacity constraints inherent in digital CIM architectures. In this paper, we present CIMFlow, an integrated framework that provides an out-of-the-box workflow for implementing and evaluating DNN workloads on digital CIM architectures. CIMFlow bridges the compilation and simulation infrastructures with a flexible instruction set architecture (ISA) design, and addresses the constraints of digital CIM through advanced partitioning and parallelism strategies in the compilation flow. Our evaluation demonstrates that CIMFlow enables systematic prototyping and optimization of digital CIM architectures across diverse configurations, providing researchers and designers with an accessible platform for extensive design space exploration.
Paper Structure (14 sections, 7 figures, 1 table, 1 algorithm)

This paper contains 14 sections, 7 figures, 1 table, 1 algorithm.

Table of Contents

  1. Introduction
  2. Background and Motivation
  3. Digital CIM Preliminaries
  4. Related Works and Our Motivation
  5. CIMFlow Framework
  6. Framework Overview
  7. ISA Design
  8. Compilation Flow
  9. Simulator Design
  10. Experimental Results
  11. Experimental Setup
  12. Compilation Optimization Evaluation
  13. Architectural Configuration Exploration
  14. Conclusion and Future Work

Figures (7)

  • Figure 1: Comparing CIMFlow with recent design and evaluation frameworks for CIM architectures.
  • Figure 2: Overview of the CIMFlow framework.
  • Figure 3: Hardware abstraction and instruction design in the CIMFlow ISA.
  • Figure 4: Compilation flow and mapping optimization strategies in CIMFlow.
  • Figure 5: Normalized speed and energy comparison of different compilation optimization strategies across DNN models.
  • ...and 2 more figures