Computing with Printed and Flexible Electronics

TL;DR

This paper surveys the landscape of printed and flexible electronics (PFE) as a low-cost, conformal alternative to silicon for extreme-edge computing. It details technology and fabrication advances, including Pragmatic's FlexIC Gen3 IGZO-TFTs on ultra-thin polyimide, and printing methods that enable additively manufactured, low-cost circuits. The authors review computing architectures ranging from natively flexible general-purpose cores to domain-specific digital and analog processing elements, highlighting bespoke and approximate ML classifiers, as well as energy-efficient pNCs and temporal processing pNCs. Reliability is addressed through robustness-aware training, fault analysis, and automatic test pattern generation, supporting the potential of PFE to achieve competitive hardware efficiency at the edge while enabling new application domains. The work argues for continued cross-layer optimization and STCO to scale these technologies toward practical deployment in wearables, packaging, and smart sensing networks.

Abstract

Printed and flexible electronics (PFE) have emerged as the ubiquitous solution for application domains at the extreme edge, where the demands for low manufacturing and operational cost cannot be met by silicon-based computing. Built on mechanically flexible substrates, printed and flexible devices offer unparalleled advantages in terms of form factor, bio-compatibility and sustainability, making them ideal for emerging and uncharted applications, such as wearable healthcare products or fast-moving consumer goods. Their desirable attributes stem from specialized fabrication technologies, e.g., Pragmatic's FlexIC, where advancements like ultra-thin substrates and specialized printing methods expand their hardware efficiency, and enable penetration to previously unexplored application domains. In recent years, significant focus has been on machine learning (ML) circuits for resource-constrained on-sensor and near-sensor processing, both in the digital and analog domains, as they meet the requirements of target applications by PFE. Despite their advancements, challenges like reliability, device integration and efficient memory design are still prevalent in PFE, spawning several research efforts towards cross-layer optimization and co-design, whilst showing promise for advancing printed and flexible electronics to new domains.

Figures (11)

• Figure 1: A flexible wafer on a polyimide substrate, and a FlexIC held in a tweezer
• Figure 2: Illustration of printed manufacturing techniques. (a) Subtractive and (b) additive processes, (c) inkjet and (d) gravure printing.
• Figure 3: Block diagram of fully-parallel bespoke MLP.
• Figure 4: Accuracy-area trade-offs among existing approaches in PFE, across commonly-used datasets.
• Figure 5: Schematics of (a) 3-bit Flash ADC Afentaki:ESL2024, and (b) its bespoke pruned counterpart Duarte:ASPDAC2025.