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Coyote v2: Raising the Level of Abstraction for Data Center FPGAs

Benjamin Ramhorst, Dario Korolija, Maximilian Jakob Heer, Jonas Dann, Luhao Liu, Gustavo Alonso

TL;DR

Coyote v2 addresses the integration bottleneck of data-center FPGAs by introducing a three-layer, hierarchical shell with runtime service reconfiguration, multithreading, and a unified interface. It decouples services from the static layer, provides a Linux device driver and high-level C++ API, and enables dynamic, fair sharing among multiple vFPGAs with RoCEv2 networking and shared virtual memory. Empirical results show 15–20% faster synthesis and order-of-magnitude faster shell/runtime reconfiguration, demonstrated on workloads including AES, HyperLogLog, and neural networks, with seamless Python-based deployment via hls4ml. This work advances FPGA deployment in data centers by delivering hardware-software abstractions, scalable memory and networking, and practical integration with host systems and accelerators.

Abstract

In the trend towards hardware specialization, FPGAs play a dual role as accelerators for offloading, e.g., network virtualization, and as a vehicle for prototyping and exploring hardware designs. While FPGAs offer versatility and performance, integrating them in larger systems remains challenging. Thus, recent efforts have focused on raising the level of abstraction through better interfaces and high-level programming languages. Yet, there is still quite some room for improvement. In this paper, we present Coyote v2, an open source FPGA shell built with a novel, three-layer hierarchical design supporting dynamic partial reconfiguration of services and user logic, with a unified logic interface, and high-level software abstractions such as support for multithreading and multitenancy. Experimental results indicate Coyote v2 reduces synthesis times between 15% and 20% and run-time reconfiguration times by an order of magnitude, when compared to existing systems. We also demonstrate the advantages of Coyote v2 by deploying several realistic applications, including HyperLogLog cardinality estimation, AES encryption, and neural network inference. Finally, Coyote v2 places a great deal of emphasis on integration with real systems through reusable and reconfigurable services, including a fully RoCE v2-compliant networking stack, a shared virtual memory model with the host, and a DMA engine between FPGAs and GPUs. We demonstrate these features by, e.g., seamlessly deploying an FPGA-accelerated neural network from Python.

Coyote v2: Raising the Level of Abstraction for Data Center FPGAs

TL;DR

Coyote v2 addresses the integration bottleneck of data-center FPGAs by introducing a three-layer, hierarchical shell with runtime service reconfiguration, multithreading, and a unified interface. It decouples services from the static layer, provides a Linux device driver and high-level C++ API, and enables dynamic, fair sharing among multiple vFPGAs with RoCEv2 networking and shared virtual memory. Empirical results show 15–20% faster synthesis and order-of-magnitude faster shell/runtime reconfiguration, demonstrated on workloads including AES, HyperLogLog, and neural networks, with seamless Python-based deployment via hls4ml. This work advances FPGA deployment in data centers by delivering hardware-software abstractions, scalable memory and networking, and practical integration with host systems and accelerators.

Abstract

In the trend towards hardware specialization, FPGAs play a dual role as accelerators for offloading, e.g., network virtualization, and as a vehicle for prototyping and exploring hardware designs. While FPGAs offer versatility and performance, integrating them in larger systems remains challenging. Thus, recent efforts have focused on raising the level of abstraction through better interfaces and high-level programming languages. Yet, there is still quite some room for improvement. In this paper, we present Coyote v2, an open source FPGA shell built with a novel, three-layer hierarchical design supporting dynamic partial reconfiguration of services and user logic, with a unified logic interface, and high-level software abstractions such as support for multithreading and multitenancy. Experimental results indicate Coyote v2 reduces synthesis times between 15% and 20% and run-time reconfiguration times by an order of magnitude, when compared to existing systems. We also demonstrate the advantages of Coyote v2 by deploying several realistic applications, including HyperLogLog cardinality estimation, AES encryption, and neural network inference. Finally, Coyote v2 places a great deal of emphasis on integration with real systems through reusable and reconfigurable services, including a fully RoCE v2-compliant networking stack, a shared virtual memory model with the host, and a DMA engine between FPGAs and GPUs. We demonstrate these features by, e.g., seamlessly deploying an FPGA-accelerated neural network from Python.
Paper Structure (28 sections, 12 figures, 3 tables)

This paper contains 28 sections, 12 figures, 3 tables.

Table of Contents

  1. Introduction
  2. Background & Motivation
  3. Related Work
  4. Requirements & Motivation
  5. System Overview
  6. Shell Reconfiguration
  7. Static Layer
  8. CPU-FPGA Link
  9. Device Driver
  10. Reconfiguration Controller
  11. Dynamic Layer
  12. Memory Management
  13. Networking
  14. Multi-tenant Fair Sharing
  15. Application Layer
  16. ...and 13 more sections

Figures (12)

  • Figure 1: Example of a multi-threaded application with four pipeline stages in hardware and each stage independently processing the data of a client.
  • Figure 2: Limitations of existing shell interfaces and the proposed solutions with Coyote v2's interfaces.
  • Figure 3: Coyote v2 system overview and project structure.
  • Figure 4: Shell reconfiguration example.
  • Figure 5: In- and outgoing vFPGA interfaces.
  • ...and 7 more figures