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Device-Algorithm Co-Design of Ferroelectric Compute-in-Memory In-Situ Annealer for Combinatorial Optimization Problems

Yu Qian, Xianmin Huang, Ranran Wang, Zeyu Yang, Min Zhou, Thomas Kämpfe, Cheng Zhuo, Xunzhao Yin

TL;DR

The paper tackles the heavy hardware cost of solving combinatorial optimization problems by reformulating COPs into an incremental-E form and implementing the computation in a ferroelectric compute-in-memory crossbar. The core advances are (1) an incremental-E transformation that reduces VMV complexity from $O(n^2)$ to $O(n)$ and replaces the exponential annealing term with a fractional factor, (2) a DG FeFET-based CiM crossbar that computes the $E_{inc}$ form in-situ, and (3) a tunable back-gate–driven in-situ annealing flow that emulates temperature decay during annealing. Empirical results on 30 Max-Cut instances with node counts from 800 to 3000 show energy reductions of $410\times$ to $1706\times$, time reductions of $7.98\times$ to $8.15\times$, and an average success rate of $98\%$, outperforming two state-of-the-art CiM annealers. This device–algorithm co-design promises scalable, energy-efficient COP solvers with high robustness, leveraging the BG-tunable DG FeFET to perform in-situ computations and annealing steps entirely within the memory hardware.

Abstract

Combinatorial optimization problems (COPs) are crucial in many applications but are computationally demanding. Traditional Ising annealers address COPs by directly converting them into Ising models (known as direct-E transformation) and solving them through iterative annealing. However, these approaches require vector-matrix-vector (VMV) multiplications with a complexity of $O(n^2)$ for Ising energy computation and complex exponential annealing factor calculations during annealing process, thus significantly increasing hardware costs. In this work, we propose a ferroelectric compute-in-memory (CiM) in-situ annealer to overcome aforementioned challenges. The proposed device-algorithm co-design framework consists of (i) a novel transformation method (first to our known) that converts COPs into an innovative incremental-E form, which reduces the complexity of VMV multiplication from $O(n^2)$ to $O(n)$, and approximates exponential annealing factor with a much simplified fractional form; (ii) a double gate ferroelectric FET (DG FeFET)-based CiM crossbar that efficiently computes the in-situ incremental-E form by leveraging the unique structure of DG FeFETs; (iii) %When feasible solutions are detected, a CiM annealer that approaches the solutions of COPs via iterative incremental-E computations within a tunable back gate-based in-situ annealing flow. Evaluation results show that our proposed CiM annealer significantly reduces hardware overhead, reducing energy consumption by 1503/1716$\times$ and time cost by 8.08/8.15$\times$ in solving 3000-node Max-Cut problems compared to two state-of-the-art annealers. It also exhibits high solving efficiency, achieving a remarkable average success rate of 98\%, whereas other annealers show only 50\% given the same iteration counts.

Device-Algorithm Co-Design of Ferroelectric Compute-in-Memory In-Situ Annealer for Combinatorial Optimization Problems

TL;DR

The paper tackles the heavy hardware cost of solving combinatorial optimization problems by reformulating COPs into an incremental-E form and implementing the computation in a ferroelectric compute-in-memory crossbar. The core advances are (1) an incremental-E transformation that reduces VMV complexity from to and replaces the exponential annealing term with a fractional factor, (2) a DG FeFET-based CiM crossbar that computes the form in-situ, and (3) a tunable back-gate–driven in-situ annealing flow that emulates temperature decay during annealing. Empirical results on 30 Max-Cut instances with node counts from 800 to 3000 show energy reductions of to , time reductions of to , and an average success rate of , outperforming two state-of-the-art CiM annealers. This device–algorithm co-design promises scalable, energy-efficient COP solvers with high robustness, leveraging the BG-tunable DG FeFET to perform in-situ computations and annealing steps entirely within the memory hardware.

Abstract

Combinatorial optimization problems (COPs) are crucial in many applications but are computationally demanding. Traditional Ising annealers address COPs by directly converting them into Ising models (known as direct-E transformation) and solving them through iterative annealing. However, these approaches require vector-matrix-vector (VMV) multiplications with a complexity of for Ising energy computation and complex exponential annealing factor calculations during annealing process, thus significantly increasing hardware costs. In this work, we propose a ferroelectric compute-in-memory (CiM) in-situ annealer to overcome aforementioned challenges. The proposed device-algorithm co-design framework consists of (i) a novel transformation method (first to our known) that converts COPs into an innovative incremental-E form, which reduces the complexity of VMV multiplication from to , and approximates exponential annealing factor with a much simplified fractional form; (ii) a double gate ferroelectric FET (DG FeFET)-based CiM crossbar that efficiently computes the in-situ incremental-E form by leveraging the unique structure of DG FeFETs; (iii) %When feasible solutions are detected, a CiM annealer that approaches the solutions of COPs via iterative incremental-E computations within a tunable back gate-based in-situ annealing flow. Evaluation results show that our proposed CiM annealer significantly reduces hardware overhead, reducing energy consumption by 1503/1716 and time cost by 8.08/8.15 in solving 3000-node Max-Cut problems compared to two state-of-the-art annealers. It also exhibits high solving efficiency, achieving a remarkable average success rate of 98\%, whereas other annealers show only 50\% given the same iteration counts.
Paper Structure (13 sections, 11 equations, 10 figures, 1 table, 1 algorithm)

This paper contains 13 sections, 11 equations, 10 figures, 1 table, 1 algorithm.

Figures (10)

  • Figure 1: CiM annealer solves COPs. (a) General flow based on simulated annealing algorithm; (b) Current solvers have high complexity in CiM acceleration part, and low efficiency in digital computation part.
  • Figure 2: FeFET and DG FeFET. (a) A FeFET device with three terminals; (b) $I_D-V_G$ curves of a FeFET with programmed low/high $V_{TH}$. (c) A DG FeFET device with four terminals; (d) $I_D-V_G$ curves of the DG FeFET, where $V_{BG}$ can flexibly adjust its $V_{TH}$ after programming.
  • Figure 3: Overview of the proposed CiM annealer. (a) Incremental-E ($E_{inc}$) transformation method; (b) DG FeFET-based crossbar for $E_{inc}$ computation; (c) Tunable BG-based in-situ annealing for approaching optimal solutions.
  • Figure 4: Compared to direct-E, the incremental-E transformation reduces complexity from $O(n^2)$ to $O(n)$, condenses three steps into a single operation, and eliminates $e^x$ function.
  • Figure 5: Complexity reduction of VMV multiplication in the incremental-E transformation. After (a) $\bm{\sigma}$ is flipped to (b) $\bm{\sigma_{new}}$, $E_{new}$ has a complexity of $O(n^2)$, composing of three groups of product terms in different colors; (c) The distinct terms between $E$ and $E_{new}$ in orange are merged by diagonal symmetry, resulting in (d) $\Delta E$ with $O(n)$ complexity.
  • ...and 5 more figures