Non-Linear Modeling and Analysis of Amplifier-Less Potentiostat Architectures

TL;DR

The paper analyzes an amplifier-less potentiostat by first establishing a linear stability framework in which the discrete-time load transfer function and open-loop response reveal two poles, leading to a practical stability limit $K \le K_1$ with $K = g_{\mathrm{m,LSB}} R_{\mathrm{WE}}$ and $K_1 = 1 - e^{-T_s/\tau}$. It validates the model using both Verilog-A time-domain simulations and MATLAB frequency-domain analysis, and provides operating guidance such as a 10-bit DAC ($I_{\mathrm{LSB}} = 10$ nA) with $V_{DD}=1.2$ V and $V_{REF}=0.6$ V to achieve acceptable phase margins under various electrode loads. The nonlinear analysis employs the describing function for the comparator, enabling prediction of limit-cycle amplitude $a$ and frequency $\omega_{LimCyc}$, and showing that the nonlinear model matches time-domain results within about $20\%$. These insights enable digital compensation to mitigate nonlinear-induced measurement uncertainty and improve control of the electrode interface in electrochemical sensing systems.

Abstract

In this article, a previously published amplifier-less potentiostat architecture is further examined. Starting with a linearized model, the impact of the most important parameters is studied taking in account the electrodes-solution electrochemical interface. A detailed model is obtained and thoroughly verified, and recommended operating conditions are given for certain limit load conditions. Then, a more complete non-linear model is developed to take in account the measurement uncertainty introduced by the circuit non-linear components. This non-linear model is compared to a time domain description of the circuit and it is verified that it can predict the non-linear behavior with a precision better than 20%. This result enables the circuit designers to compensate for these effects and ultimately reduce the overall measurement uncertainty.

Figures (5)

• Figure 1: Circuit schematic of the potentiostat proposed in akram_36_2024akram_ultra-low-power_2025.
• Figure 2: Block Diagram of the system. The reference is fed to the comparator and the counter, $V_{\mathrm{RE}}$ is established as the DAC output times the load.
• Figure 3: Bode plots of the calculated transfer functions. Matlab Transfer Function (TF) and Verilog-A (SIM) for $g_\mathrm{m,LSB}=10$ nS (i.e. $I_\mathrm{LSB}=10$ nA), $R_{\mathrm{WE}}=60$ M$\Omega$, $C_{\mathrm{WE}}=1$ nF, $V_{\mathrm{REF}}=0.6$ V and changing $f_\mathrm{s}$. (a) Represents the magnitude while (b) the phase of the Bode plot.
• Figure 4: Comparison between Simulink and Verilog-A non-linear models for $g_\mathrm{m,LSB} = 125$ pS, $R_{\mathrm{WE}}=50$ M$\Omega$, $C_{\mathrm{WE}}=1$ nF, $V_\mathrm{DD} = 1.2$ V and (a) $f_\mathrm{s}=1$ kHz, (b) $f_\mathrm{s}=10$ kHz.
• Figure 5: Comparison of the non-linear model limit cycle parameters prediction with the time domain model results. (a) Amplitude. (b) Oscillation Frequency.