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Systematic Hardware Integration Testing for Smart Video-based Medical Device Prototypes

Oliver Bause, Julia Werner, Oliver Bringmann

TL;DR

This work addresses the challenge of validating real-time, camera-based in-body medical devices before clinical testing by introducing an FPGA-based hardware-in-the-loop framework. It uses an on-demand digital twin of a NanEyeC camera and pre-recorded Video Capsule Endoscopy data to emulate GI traversal and verify the full imaging pipeline, including an on-board ML accelerator. Key contributions include a modular SystemVerilog NanEyeC twin on a Digilent ZYBO, a back-end verification pipeline, and PC-to-FPGA image transmission with Quad-SPI, validated through capture-latency, fault-injection, and power-estimation experiments. The framework supports rigorous preclinical validation, potentially reducing development cycles and enabling safer integration of on-device ML components prior to clinical trials, with future work on power modeling and wireless data retrieval.

Abstract

This paper presents a hardware-in-the-loop (HIL) verification system for intelligent, camera-based in-body medical devices. A case study of a Video Capsule Endoscopy (VCE) prototype is used to illustrate the system's functionality. The field-programmable gate array (FPGA)-based approach simulates the capsule's traversal through the strointestinal (GI) tract by injecting on-demand pre-recorded images from VCE studies. It is demonstrated that the HIL configuration is capable of meeting the real-time requirements of the prototypes and automatically identifying errors. The integration of machine learning (ML) hardware accelerators within medical devices can be facilitated by utilising this configuration, as it enables the verification of its functionality prior to the initiation of clinical testing.

Systematic Hardware Integration Testing for Smart Video-based Medical Device Prototypes

TL;DR

This work addresses the challenge of validating real-time, camera-based in-body medical devices before clinical testing by introducing an FPGA-based hardware-in-the-loop framework. It uses an on-demand digital twin of a NanEyeC camera and pre-recorded Video Capsule Endoscopy data to emulate GI traversal and verify the full imaging pipeline, including an on-board ML accelerator. Key contributions include a modular SystemVerilog NanEyeC twin on a Digilent ZYBO, a back-end verification pipeline, and PC-to-FPGA image transmission with Quad-SPI, validated through capture-latency, fault-injection, and power-estimation experiments. The framework supports rigorous preclinical validation, potentially reducing development cycles and enabling safer integration of on-device ML components prior to clinical trials, with future work on power modeling and wireless data retrieval.

Abstract

This paper presents a hardware-in-the-loop (HIL) verification system for intelligent, camera-based in-body medical devices. A case study of a Video Capsule Endoscopy (VCE) prototype is used to illustrate the system's functionality. The field-programmable gate array (FPGA)-based approach simulates the capsule's traversal through the strointestinal (GI) tract by injecting on-demand pre-recorded images from VCE studies. It is demonstrated that the HIL configuration is capable of meeting the real-time requirements of the prototypes and automatically identifying errors. The integration of machine learning (ML) hardware accelerators within medical devices can be facilitated by utilising this configuration, as it enables the verification of its functionality prior to the initiation of clinical testing.
Paper Structure (12 sections, 5 figures, 1 table)

This paper contains 12 sections, 5 figures, 1 table.

Table of Contents

  1. Introduction
  2. Testing of In-Body Medical Devices
  3. Related Work
  4. Hardware-in-the-Loop Framework
  5. FPGA Design
  6. Back-End
  7. PC to FPGA Image Transmission
  8. Evaluation
  9. Capture Latency
  10. Fault Injection
  11. Power Estimation
  12. Conclusion

Figures (5)

  • Figure 1: Top level diagram of a VCE device and the proposed HIL framework.
  • Figure 2: State machine of the task of the and the back-end and the interaction between them.
  • Figure 3: Comparison of the average transmission times during a simulation of a complete study with more than 6300images with Single-, Dual-, and Quad-SPI.
  • Figure 4: Identification of excessive transmission periods that lead to corrupted images being received with their respective number of pixel deviations.
  • Figure 5: Estimation of the power consumption of the camera module at different frame rates clocked at 5