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ChipletQuake: On-die Digital Impedance Sensing for Chiplet and Interposer Verification

Saleh Khalaj Monfared, Maryam Saadat Safa, Shahin Tajik

TL;DR

ChipletQuake addresses the security challenges of chiplet-based systems by enabling post-silicon, on-die impedance sensing of the PDN to verify adjacent chiplets and interposers without additional signal interfaces. The approach uses a verifier chiplet with a frequency-sweeping actuator array and a 2D network of TDC sensors to induce and measure impedance changes, producing a unique impedance signature stored as a golden profile for remote attestation via a one-time key $K_{ver}$. It is validated on an FPGA-based multi-chiplet platform, demonstrating detection of Hardware Trojans, interposer tampering, and dormant modifications through frequency-domain impedance profiling, with rigorous statistical measures including Welch’s $t$-test and Wasserstein distance. The framework offers a practical, hardware-efficient pathway to harden chiplet/systems-in-package security, enabling robust verification in horizontal supply chains and informing future work on dynamic verification and IP fingerprinting.

Abstract

The increasing complexity and cost of manufacturing monolithic chips have driven the semiconductor industry toward chiplet-based designs, where smaller and modular chiplets are integrated onto a single interposer. While chiplet architectures offer significant advantages, such as improved yields, design flexibility, and cost efficiency, they introduce new security challenges in the horizontal hardware manufacturing supply chain. These challenges include risks of hardware Trojans, cross-die side-channel and fault injection attacks, probing of chiplet interfaces, and intellectual property theft. To address these concerns, this paper presents \textit{ChipletQuake}, a novel on-chiplet framework for verifying the physical security and integrity of adjacent chiplets during the post-silicon stage. By sensing the impedance of the power delivery network (PDN) of the system, \textit{ChipletQuake} detects tamper events in the interposer and neighboring chiplets without requiring any direct signal interface or additional hardware components. Fully compatible with the digital resources of FPGA-based chiplets, this framework demonstrates the ability to identify the insertion of passive and subtle malicious circuits, providing an effective solution to enhance the security of chiplet-based systems. To validate our claims, we showcase how our framework detects Hardware Trojan and interposer tampering.

ChipletQuake: On-die Digital Impedance Sensing for Chiplet and Interposer Verification

TL;DR

ChipletQuake addresses the security challenges of chiplet-based systems by enabling post-silicon, on-die impedance sensing of the PDN to verify adjacent chiplets and interposers without additional signal interfaces. The approach uses a verifier chiplet with a frequency-sweeping actuator array and a 2D network of TDC sensors to induce and measure impedance changes, producing a unique impedance signature stored as a golden profile for remote attestation via a one-time key . It is validated on an FPGA-based multi-chiplet platform, demonstrating detection of Hardware Trojans, interposer tampering, and dormant modifications through frequency-domain impedance profiling, with rigorous statistical measures including Welch’s -test and Wasserstein distance. The framework offers a practical, hardware-efficient pathway to harden chiplet/systems-in-package security, enabling robust verification in horizontal supply chains and informing future work on dynamic verification and IP fingerprinting.

Abstract

The increasing complexity and cost of manufacturing monolithic chips have driven the semiconductor industry toward chiplet-based designs, where smaller and modular chiplets are integrated onto a single interposer. While chiplet architectures offer significant advantages, such as improved yields, design flexibility, and cost efficiency, they introduce new security challenges in the horizontal hardware manufacturing supply chain. These challenges include risks of hardware Trojans, cross-die side-channel and fault injection attacks, probing of chiplet interfaces, and intellectual property theft. To address these concerns, this paper presents \textit{ChipletQuake}, a novel on-chiplet framework for verifying the physical security and integrity of adjacent chiplets during the post-silicon stage. By sensing the impedance of the power delivery network (PDN) of the system, \textit{ChipletQuake} detects tamper events in the interposer and neighboring chiplets without requiring any direct signal interface or additional hardware components. Fully compatible with the digital resources of FPGA-based chiplets, this framework demonstrates the ability to identify the insertion of passive and subtle malicious circuits, providing an effective solution to enhance the security of chiplet-based systems. To validate our claims, we showcase how our framework detects Hardware Trojan and interposer tampering.
Paper Structure (25 sections, 2 equations, 17 figures)

This paper contains 25 sections, 2 equations, 17 figures.

Figures (17)

  • Figure 1: A simple circuit model of a PDN and interposer inspired by hossen2022analysis.
  • Figure 2: (a) Equivalent RLC circuit model of the power distribution network of the PCB and chip. (b) Contribution of different parts of the PDN to the impedance over frequency mosavirik2023silicon.
  • Figure 3: high-level implementation of a TDC-based fault detection sensor
  • Figure 4: High-level overview of ChipletQuake functionality
  • Figure 5: Chiplet Verification Flow via Impedance Estimation
  • ...and 12 more figures