ChiseLLM: Unleashing the Power of Reasoning LLMs for Chisel Agile Hardware Development

TL;DR

ChiseLLM targets the gap in Chisel code generation by injecting domain-adapted reasoning traces through prompt-guided distillation and targeted finetuning, achieving substantial gains in syntax correctness and design variability with relatively small model sizes. By constructing high-quality, domain-specific datasets from public RTL resources and leveraging task-aware prompts, ChiseLLM adapts reasoning patterns to hardware design tasks, closing the gap between open-source models and commercial benchmarks. The approach delivers robust improvements across Spec-to-Chisel and Decompile-to-Chisel tasks, demonstrates strong design variability capabilities, and provides open-source datasets and models to catalyze further research in LLM-assisted HCL-based Agile Hardware Development. This work lays a foundation for scalable, cost-effective HCL generation and design space exploration using domain-adapted LLMs.

Abstract

The growing demand for Domain-Specific Architecture (DSA) has driven the development of Agile Hardware Development Methodology (AHDM). Hardware Construction Language (HCL) like Chisel offers high-level abstraction features, making it an ideal language for HCL-Based AHDM. While Large Language Models (LLMs) excel in code generation tasks, they still face challenges with Chisel generation, particularly regarding syntax correctness and design variability. Recent reasoning models have significantly enhanced code generation capabilities through test-time scaling techniques. However, we found that reasoning models without domain adaptation cannot bring substantial benefits to Chisel code generation tasks. This paper presents ChiseLLM, a solution comprising data processing and transformation, prompt-guided reasoning trace synthesis, and domain-adapted model training. We constructed high-quality datasets from public RTL code resources and guided the model to adopt structured thinking patterns through prompt enhancement methods. Experiments demonstrate that our ChiseLLM-7B and ChiseLLM-32B models improved syntax correctness by 18.85% and 26.32% respectively over base models, while increasing variability design ability by 47.58% compared to baseline reasoning models. Our datasets and models are publicly available, providing high-performance, cost-effective models for HCL-Based AHDM, and offering an effective baseline for future research. Github repository: https://github.com/observerw/ChiseLLM

Figures (6)

• Figure 1: An overview diagram of the construction of the ChiseLLM datasets and models, including Source Data Processing & Synthesing, Prompt-Guided Reasoning Trace Generation and Reasoning Model Finetuning.
• Figure 2: Diagrams related to the ChiseLLM data processing and distillation workflow. Figure (a) illustrate the process of collecting and processing the source data. Figure (b) includes the prompt template used for prompt-guided distillation. Figure (c) shows the statistical characteristics of the ChiseLLM-{Completion,Decompile} datasets.
• Figure 3: Schematic diagrams of the three types of design variant. Practical examples of functional variants are shown in detail in the figure.
• Figure 4: Variability design capability of different models on the RTLLM dataset when performing Decompile-to-Chisel tasks. The blue bar represents the open-source reasoning and non-reasoning baseline models. The green bar represents the ChiseLLM-32B model. The red bars represent the commercial models. Each bar is distinctively hatched with different patterns.
• Figure 5: An actual example of ChiseLLM-32B and Qwen2.5-32B-Coder-Instruct decompiling Verilog source code. The gray part represents the Verilog source code, the blue part represents the Chisel module generated by the Qwen model, and the green part represents the Chisel module generated by the ChiseLLM model. The content within the <think> tags represents the thinking process of the ChiseLLM model during decompilation, which, due to its length, is summarized as a numbered list in the figure. The ChiseLLM model follows a structured reasoning process during decompilation, ultimately producing a Chisel module with higher variability and functional extensibility.