Scaling Data Center TCP to Terabits with Laminar

TL;DR

Laminar tackles the challenge of scaling TCP in data centers to terabit speeds by offloading the transport logic to the programmable match-action-based RMT architecture. It rethinks TCP as a low-overhead, single-pass pipeline with optimistic concurrency and pseudo-segment updates, enabling line-rate processing while preserving standard TCP semantics and POSIX compatibility. Through a comprehensive prototype on Intel Tofino2 and an FPGA-based SmartNIC port, Laminar demonstrates RDMA-like throughput and latency across RPCs, streaming workloads, and storage interfaces, with significant gains in efficiency and scalability over Linux and TAS baselines. The work also showcases flexibility via extensions such as a shared log sequencer and Timely congestion control, and demonstrates generalizability to future hardware, including FPGA-based implementations, laying a foundation for next-generation SmartNICs and data-center networks.

Abstract

Laminar is the first TCP stack designed for the reconfigurable match-action table (RMT) architecture, widely used in high-speed programmable switches and SmartNICs. Laminar reimagines TCP processing as a pipeline of simple match-action operations, enabling line-rate performance with low latency and minimal energy consumption, while maintaining compatibility with standard TCP and POSIX sockets. Leveraging novel techniques like optimistic concurrency, pseudo segment updates, and bump-in-the-wire processing, Laminar handles the transport logic, including retransmission, reassembly, flow, and congestion control, entirely within the RMT pipeline. We prototype Laminar on an Intel Tofino2 switch, and demonstrate its scalability to terabit speeds, its flexibility, and robustness to network dynamics. Laminar delivers RDMA-equivalent performance, saving up to 16 host CPU cores versus the TAS kernel-bypass TCP stack with short RPC workloads, achieving 1.3$\times$ higher peak throughput at 5$\times$ lower 99.99p tail latency. At scale, Laminar drives nearly $1$Bpps of TCP processing while keeping RPC tail latency near $20μs$. For streaming workloads, Laminar achieves $25$Mpps per-core, enough to saturate the line-rate. It significantly benefits real applications: a key-value store on Laminar doubles throughput-per-watt while maintaining a 99.99p tail latency lower than TAS's best case tail latency, and SPDK's NVMe-oTCP reaches RDMA-level efficiency. Demonstrating Laminar's flexibility, we implement TCP stack extensions, including a sequencer API for a linearizable distributed shared log, Timely congestion control, and delayed ACKs. Finally, Laminar generalizes to FPGA SmartNICs, delivering $3\times$ ToNIC's packet rate under equal timing.

Figures (14)

• Figure 1: TAS TCP connection state and dependencies.
• Figure 2: Laminar overview. The RMT TCP transport logic in 6 is our focus (§\ref{['sec:lock-free-sync']}).
• Figure 3: RMT TCP segment reassembly paths.
• Figure 4: RMT TCP processing for TX workflow.
• Figure 5: RMT TCP processing path for RX workflow.