Apollo: Automated Routing-Informed Placement for Large-Scale Photonic Integrated Circuits

TL;DR

Apollo tackles the scalability gap in photonic IC design by tightly integrating waveguide routing constraints into placement. It introduces cosWA, a routing-aware wirelength, a routing-informed net spacing model, and a density-regularized objective, all optimized with a blockwise adaptive Nesterov method and progressive constraint projection. The framework, built on GPU-accelerated DREAMPlace foundations, achieves high routability (average ~94.8% across large benchmarks) with reduced crossings and fast runtimes, outperforming prior methods. By coupling placement with physical routing and offering open benchmarks, Apollo provides a practical, scalable solution for next-generation EPDA flows in large-scale PICs.

Abstract

As technology advances, photonic integrated circuits (PICs) are rapidly scaling in size and complexity, with modern designs integrating thousands of components. However, the analog custom layout nature of photonics, the curvy waveguide structures, and single-layer routing resources impose stringent physical constraints, such as minimum bend radii and waveguide crossing penalties, which make manual layout the de facto standard. This manual process takes weeks to complete and is error-prone, which is fundamentally unscalable for large-scale PIC systems. Existing automation solutions have adopted force-directed placement on small benchmarks with tens of components, with limited routability and scalability. To fill this fundamental gap in the electronic-photonic design automation (EPDA) toolchain, we present the first GPU-accelerated, routing-informed placement framework. It features an asymmetric bending-aware wirelength function with explicit modeling of waveguide routing congestion and crossings for routability maximization. Meanwhile, conditional projection is employed to gradually enforce a variety of user-defined layout constraints, including alignment, spacing, etc. This constrained optimization is accelerated and stabilized by a custom blockwise adaptive Nesterov-accelerated optimizer, ensuring stable and high-quality convergence. Compared to existing methods, our method can generate high-quality layouts for large-scale PICs with an average routing success rate of 94.79% across all benchmarks within minutes. By tightly coupling placement with physical-aware routing, our method establishes a new paradigm for automated PIC design, bringing intelligent, scalable layout synthesis to the forefront of next-generation EPDA. Our code is open-sourced at https://github.com/ScopeX-ASU/Apollo.

Figures (8)

• Figure 1: Solutions with the same HPWL give different waveguide routing and total bending angles.
• Figure 2: Proposed bending-aware wirelength function: detour region results in larger wirelength cost.
• Figure 3: Illustration of the critical spacing requirements in PIC routing that should be considered during placement.
• Figure 4: Common physical design constraints in PICs.
• Figure 5: Placement animation of Apollo on ADEPT_16x16.