CMOS-compatible processing and room-temperature characterization on wafer-level for scalable quantum computing

TL;DR

This work addresses the scalability bottleneck of superconducting qubits by demonstrating CMOS-compatible fabrication on a 200 mm wafer and wafer-scale room-temperature characterization that predicts cryogenic qubit performance. The authors integrate an industry-grade fabrication flow with a process-control monitoring array (test junctions and shorts) and apply the Ambegaokar-Baratoff model to relate RT resistance to qubit frequency, achieving a functional-device yield of $Y_R=92.8\%$ and guiding pre-selection before cooldown. Cryogenic tests on 40 qubits across the wafer yield $T_1$ times up to $80\,\mu$s, $T_2^*>100\,\mu$s, and single-qubit gate fidelities $>99.6\%$, with a measured frequency spread of roughly $8.4\%$ and a Tc around $0.71$ K from RT-to-cryogenic fits. Collectively, the results demonstrate the viability of industry-style, wafer-scale qubit fabrication and rapid RT screening to enable scalable, 3D-integrated quantum processing units.

Abstract

We report on an industry-grade CMOS-compatible qubit fabrication approach using a CMOS pilot line, enabling a yield of functional devices reaching 92.8 %, with a resistance spread evaluated across the full wafer 200 mm diameter of 12.4 % and relaxation times (T1) approaching 80 us. Furthermore, we conducted a comprehensive analysis of wafer-scale room temperature (RT) characteristics collected from multiple wafers and fabrication runs, focusing on RT measurements and their correlation to low temperature qubit parameters. From defined test structures, an across-wafer Josephson junction (JJ) area variation of 10.1 % and oxide barrier variation of 7.2 % was calculated. Additionally, from the room-temperature JJ characterization the qubit frequency can be derived on wafer-level applying the Ambegaokar-Baratoff model before low temperature measurements. This sets the stage for pre-cooldown wafer-level JJ evaluation and sorting. In particular, such early-on device characterization and validation are crucial for increasing the fabrication yield and qubit frequency targeting, which currently represent major scaling challenges. Furthermore, it enables the fabrication of large multichip quantum systems in the future. Our analysis highlight the great potential of CMOS-compatible industry-style fabrication of superconducting qubits for scalable quantum computing in a foundry pilot line cleanroom.

Figures (8)

• Figure 1: a. 200 mm qubit wafer with 106 dies. b. Layout of a single die with qubits and test structures. c. SEM image of a qubit’s JJ. d. Electron microscopy image of the cross section of a JJ.
• Figure 2: Qubit fabrication schematic: a. structuring of BE based on Al (grey) on Si (purple), b. Ar ion milling of BE to remove native oxide, c. static oxidation of BE to form junction oxide, d. capping with top Al layer (dark grey), e. structuring of TE.
• Figure 3: a. Normalized resistance ($R/\bar{R}$) histograms obtained for BE shorts (width of 350 nm and $RSD_\text{w}^{\text{BE}}$ = 8.8 %) and for TE shorts(width of 500 nm and $RSD_\text{w}^{\text{TE}}$ = 5.3 %). b. design width $w_D$ vs. across-wafer inverse resistance mean 1/$\bar{R}$. With a linear fit, the offset $\Delta \text{w}$ between design and fabrication width can be extracted by the crossing at the y-axis (zoomed in). c. Normalized sheet resistance map ($R_\square/\bar{R}_\square$) from a 49-point 4pp measurement on a 150 nm thick Al layer, showing a relative standard deviation of $RSD_{\text{R}_\square}$ = 1.4 %.
• Figure 4: histogram (a.) and yield wafer map (b.) of $R_{\text{JJ}}$ with junction area of 0.175 µm$^2$ across wafer with specification 100 $\Omega < R_{\text{JJ}} < 50$ k$\Omega$.
• Figure 5: a. Typical IV-curve recorded for the test junctions of size 0.175 µm$^2$ with direct (red) tunneling and trap assisted (blue) tunneling with $m$ = 2.75 before the breakthrough at 1.2 V. A value of $R_{\text{JJ}}$ = 7.1 k$\Omega$ was measured in the direct tunneling regime. b. Histogram of $V_{\text{BT}}$ for different junction sizes.