VeriCoder: Enhancing LLM-Based RTL Code Generation through Functional Correctness Validation

TL;DR

VeriCoder tackles the gap in RTL code generation by training on a large functionally validated dataset created through a teacher-LLM guided unit-test generation and refinement loop. The approach yields a 125,777-example dataset of NL specifications, RTL implementations, and passing tests, enabling LoRA-finetuning of a 14B-instruct model that achieves state-of-the-art results on VerilogEval and RTLLM. An ablation shows that functionally validated data significantly improves performance over non-validated data, underscoring the importance of dataset quality. While open-source models still lag behind top commercial LLMs, VeriCoder demonstrates the practical viability of functional validation and points to formal verification and RL as promising future enhancements for robust RTL code generation.

Abstract

Recent advances in Large Language Models (LLMs) have sparked growing interest in applying them to Electronic Design Automation (EDA) tasks, particularly Register Transfer Level (RTL) code generation. While several RTL datasets have been introduced, most focus on syntactic validity rather than functional validation with tests, leading to training examples that compile but may not implement the intended behavior. We present VERICODER, a model for RTL code generation fine-tuned on a dataset validated for functional correctness. This fine-tuning dataset is constructed using a novel methodology that combines unit test generation with feedback-directed refinement. Given a natural language specification and an initial RTL design, we prompt a teacher model (GPT-4o-mini) to generate unit tests and iteratively revise the RTL design based on its simulation results using the generated tests. If necessary, the teacher model also updates the tests to ensure they comply with the natural language specification. As a result of this process, every example in our dataset is functionally validated, consisting of a natural language description, an RTL implementation, and passing tests. Fine-tuned on this dataset of 125,777 examples, VERICODER achieves state-of-the-art metrics in functional correctness on VerilogEval and RTLLM, with relative gains of up to 71.7% and 27.4%, respectively. An ablation study further shows that models trained on our functionally validated dataset outperform those trained on functionally non-validated datasets, underscoring the importance of high-quality datasets in RTL code generation. Our code, data, and models are publicly available at https://github.com/Anjiang-Wei/VeriCoder

Figures (4)

• Figure 1: LLM-guided dataset augmentation overview.
• Figure 2: Natural language specification (left) and the corresponding buggy and corrected Verilog designs (middle and right). The specification and buggy design are from the original dataset cui2024origen, which lacks tests, while the test (\ref{['fig:test']}) and corrected design are generated by a teacher model (GPT-4o-mini) and included in our validated dataset.
• Figure 3: Unit test for the and3 module. The buggy design (\ref{['fig:buggy']}) times out on this test, while the corrected design (\ref{['fig:fixed']}) passes successfully. The test is generated by the teacher model GPT-4o-mini using the prompt in \ref{['fig:testprompt']}, and is used to validate and augment the original dataset, which contains no tests.
• Figure 4: Prompt templates provided to the teacher model for automated Verilog test generation and refinement, ensuring that the final design passes the generated test and matches the original natural language specification.