Can we build a transistor using vacancy-induced bound states in a topological insulator

TL;DR

The paper tackles realizing an open-circuit/closed-circuit switch in two-dimensional topological insulators by engineering a gap between edge- and bulk-like states through vacancy-induced edge states. A 1D chain of vacancies provides the conducting channel while a perpendicular vacancy gate modulates local electron density to shift the quasi-Fermi level $E_F^* = E_F + k_B T \ln(\rho/\rho_0)$ into the gap for off switching. Band-structure validation via the Haldane lattice model shows vacancy-induced edge states residing in the center of the topological gap and isolated from bulk states, and DFT simulations demonstrate gate-induced depletion of edge-state density and suppression of inter-vacancy hopping $t_m$. If realized, this vacancy-based TI FET could enable atomic-scale, low-power logic circuits, but it requires further simulation and experimental confirmation of efficiency, gate stability, and practical vacancy-chain fabrication.

Abstract

Topological insulators (TIs) have been considered as promising candidates for next generation of electronic devices due to their topologically protected quantum transport phenomena. In this work, a scheme for atomic-scale field effect transistor (FET) based on vacancy-induced edge states in TIs is promoted. By designing the positions of vacancies, the closed channel between source and drain terminals provided by vacancy-induced edge states can have the energy spectra with a gap between edge and bulk states. When gate terminal receive the signal, electric field applied by gate terminal can shift quasi Fermi energy of the closed channel from edge states into the gap, and hence open the channel between source and drain terminals. The energy spectra and the effect of electric field are demonstrated using Haldane model and density functional theory (DFT) respectively. This work suggest possible revolutionary applicational potentials of vacancy-induced edge states in topological insulators for atomic-scale electronics.

Figures (4)

• Figure 1: a, schematically showing the mechanism of semiconductor junction FET. Lighter blue regions are P-type semiconductor connected with gate terminal and the white region is N-type semiconductor connecting source and drain terminals. The quasi Fermi level ($E_F^*$) of electrons intersects with conduction band in N-type semiconductor under closed circuit condition, and lies in band gap away from conduction band under open circuit condition. $E_c$ and $E_v$ are the energy of conduction band and valance band respectively. b, the scheme of FET in TIs using topological states. The energy bands must have a topological energy gap (white area) between valance and conduction bulk states (gray area). The topological edge states (lighter red area) in topological energy gap making closed circuit between source and drain terminals when there is no voltage on gate terminal. Under the opposite situation, the electric field applied through gate terminal will shift the quasi Fermi level ($E_F^*$) into topological energy gap between edge states and bulk states, and hence leads to open circuit between source and drain terminals.
• Figure 2: The structure and energy bands of a vacancies' chain. a, the structure of super cell of Haldane model. $\boldsymbol{a}_1$ and $\boldsymbol{a}_2$ are super cell lattice vectors. The big and small black dots are A and B type of atoms. Black and gray bounds between atoms indicate the nearest neighbor hopping and the next nearest hopping respectively. The lighter red cloud indicates position of vacancy and associated edge mode around. b, energy band structure of the super cell. Gray and lighter red area indicate bulk and edge states induced by vacancies respectively. The thin dashed line above the red topological edge band is predicted by the effective Hamiltonian in the dashed box. The effective Hamiltonian consider hopping of vacancy induced edge state to its neighbor site on a chain of vacancies with hopping rate $t_m$.
• Figure 3: The structure of FET in TIs using vacancies induced edge states. A chain of vacancies can be used as wire connecting source and drain terminals. The gate terminal can also made by vacancies but spacing with a layer of vacancies-free topological insulator. The layer of vacancies-free area allow the field of gate terminal affecting states on the chain of vacancies but avoid breakdown.
• Figure 4: The effects of electric field on the distribution of carriers of vacancies induced edge states. a, contour map of the ground state carriers' distribution of vacancies induced edge states without electric field (blue) and under uniform electric field (red) obtained using density functional theory simulation. The density have been normalized to $1$, $\int \rho (x,y) dxdy = 1$. Contour levels are logarithm density, $\mathrm{log}_{10} \rho$. The area in dashed box is enlarged in right top. For obtaining red dashed ground state in this panel, $E_y = 0.15$ is used. b, the overlap density in function of relative electric field intensity. The overlap $S$ is defined as density of carriers under the gray area between two vacancies, $S = \int_{gray} \rho (x,y) dxdy$, which determines if current are allowed moving from one vacancy to another. The relative electric field intensity is defined as $V_E / V_0$, $V_E = E_y L_y$ is the depth of electric potential and $V_0$ is the depth of vacancy's potential which reflect the robustness of states induced by vacancies. In the simulation, $L_x = 10$ and $V_0 = 10$ are used.