ReasoningV: Efficient Verilog Code Generation with Adaptive Hybrid Reasoning Model

TL;DR

ReasoningV tackles the challenges of Verilog generation by combining a high-quality reasoning dataset, a targeted two-stage training regimen, and an adaptive reasoning mechanism. It demonstrates that data quality and deep hardware reasoning can be achieved with modest compute by separating foundational knowledge learning from deep reasoning, then refining inference with complexity-aware budgeting. On VerilogEval-human, ReasoningV achieves $57.8\%$ pass@1 and outperforms open-source baselines by $10.4\%$, with $73.6\%$ on VerilogEval-machine and $44.6\%$ on RTLLM, while token usage is reduced by up to $78\%$ via adaptive reasoning. These results provide a practical path toward reliable, resource-efficient AI-assisted hardware design automation, with public release of code and data to foster further development.

Abstract

Large Language Models (LLMs) have advanced Verilog code generation significantly, yet face challenges in data quality, reasoning capabilities, and computational efficiency. This paper presents ReasoningV, a novel model employing a hybrid reasoning strategy that integrates trained intrinsic capabilities with dynamic inference adaptation for Verilog code generation. Our framework introduces three complementary innovations: (1) ReasoningV-5K, a high-quality dataset of 5,000 functionally verified instances with reasoning paths created through multi-dimensional filtering of PyraNet samples; (2) a two-stage training approach combining parameter-efficient fine-tuning for foundational knowledge with full-parameter optimization for enhanced reasoning; and (3) an adaptive reasoning mechanism that dynamically adjusts reasoning depth based on problem complexity, reducing token consumption by up to 75\% while preserving performance. Experimental results demonstrate ReasoningV's effectiveness with a pass@1 accuracy of 57.8\% on VerilogEval-human, achieving performance competitive with leading commercial models like Gemini-2.0-flash (59.5\%) and exceeding the previous best open-source model by 10.4 percentage points. ReasoningV offers a more reliable and accessible pathway for advancing AI-driven hardware design automation, with our model, data, and code available at https://github.com/BUAA-CLab/ReasoningV.

Figures (4)

• Figure 1: Overall architecture of the ReasoningV framework.
• Figure 2: Multi-stage data filtering pipeline for ReasoningV-5K dataset construction.
• Figure 3: Verilog Reasoning Path and Testbench Generation.
• Figure 4: Pass@1 Performance vs. Model Size on VerilogEval-Human.