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Exploring unique design features of the Monolithic Stitched Sensor with Timing (MOST): yield, powering, timing, and sensor reverse bias

Mariia Selina, R. Barthel, S. Bugiel, L. Cecconi, J. De Melo, M. Fransen, A. Grelli, I. Hobus, A. Isakov, A. Junique, P. Leitao, M. Mager, Y. Otarid, F. Piro, M. J. Rossewij, S. Solokhin, J. Sonneveld, W. Snoeys, N. Tiltmann, A. Vitkovskiy, H. Wennloef

TL;DR

This work evaluates the Monolithic Stitched Sensor with Timing (MOST) as an evolution of stitched CMOS sensors for the ALICE ITS3 upgrade, focusing on granular power gating, asynchronous hit-based readout, and a front-end–driven reverse-bias scheme. MOST demonstrates high per-pixel yield (>99.98%) across multiple chips and shows that fine-grained power switches can isolate faults while preserving density. Timing tests reveal an on-chip calibration jitter as low as ~12 ps over long transmission distances, with the readout path exhibiting larger jitter that warrants further study, confirming the viability of timing-preserving, high-density monolithic sensors. These results support the feasibility of timing-enabled ITS3 devices and inform next steps involving parameter optimization and beam-test validation to quantify efficiency and spatial resolution.

Abstract

Monolithic stitched CMOS sensors are explored for the upgrade of Inner Tracking System of the ALICE experiment (ITS3) and the R&D of the CERN Experimental Physics Department. To learn about stitching, two 26 cm long stitched sensors, the Monolithic Stitched Sensor (MOSS), and the Monolithic Stitched Sensor with Timing (MOST), were implemented in the Engineering Round 1 (ER1) in the TPSCo 65nm ISC technology. Contrary to the MOSS, powered by 20 distinct power domains accessible from separate pads, the MOST has one global analog and digital power domain to or from which small fractions of the matrix can be connected or disconnected by conservatively designed power switches to prevent shorts or defects from affecting the full chip. Instead of the synchronous readout in the MOSS, the MOST immediately transfers hit information upon a hit, preserving timing information. The sensor reverse bias is also applied through the bias of the front-end rather than by a reverse substrate bias. This paper presents the first characterization results of the MOST, with the focus on its specific characteristics, including yield analysis, precise timing measurements, and the potential of its alternative biasing approach for improved sensor performance.

Exploring unique design features of the Monolithic Stitched Sensor with Timing (MOST): yield, powering, timing, and sensor reverse bias

TL;DR

This work evaluates the Monolithic Stitched Sensor with Timing (MOST) as an evolution of stitched CMOS sensors for the ALICE ITS3 upgrade, focusing on granular power gating, asynchronous hit-based readout, and a front-end–driven reverse-bias scheme. MOST demonstrates high per-pixel yield (>99.98%) across multiple chips and shows that fine-grained power switches can isolate faults while preserving density. Timing tests reveal an on-chip calibration jitter as low as ~12 ps over long transmission distances, with the readout path exhibiting larger jitter that warrants further study, confirming the viability of timing-preserving, high-density monolithic sensors. These results support the feasibility of timing-enabled ITS3 devices and inform next steps involving parameter optimization and beam-test validation to quantify efficiency and spatial resolution.

Abstract

Monolithic stitched CMOS sensors are explored for the upgrade of Inner Tracking System of the ALICE experiment (ITS3) and the R&D of the CERN Experimental Physics Department. To learn about stitching, two 26 cm long stitched sensors, the Monolithic Stitched Sensor (MOSS), and the Monolithic Stitched Sensor with Timing (MOST), were implemented in the Engineering Round 1 (ER1) in the TPSCo 65nm ISC technology. Contrary to the MOSS, powered by 20 distinct power domains accessible from separate pads, the MOST has one global analog and digital power domain to or from which small fractions of the matrix can be connected or disconnected by conservatively designed power switches to prevent shorts or defects from affecting the full chip. Instead of the synchronous readout in the MOSS, the MOST immediately transfers hit information upon a hit, preserving timing information. The sensor reverse bias is also applied through the bias of the front-end rather than by a reverse substrate bias. This paper presents the first characterization results of the MOST, with the focus on its specific characteristics, including yield analysis, precise timing measurements, and the potential of its alternative biasing approach for improved sensor performance.

Paper Structure

This paper contains 5 sections, 5 figures.

Table of Contents

  1. Introduction
  2. Highly granular powering scheme using power switches and dense matrix circuitry
  3. Timing Capabilities with Asynchronous Readout
  4. Alternative Sensor Biasing Scheme
  5. Conclusion and Outlook

Figures (5)

  • Figure 1: MOST Layout of a group of 4 pixels piro_front-end_nodate.
  • Figure 2: Graph on the left showing the increase in power consumption of the chip with the number of pixels powered on. On the right there is first evaluation of the individual pixel yield for 4 chips or 40 stitched units (SU): the average number of non-fully responsive pixels per stitched unit is 15 per 90112 pixels, indicating a pixel yield better than 99.98%.
  • Figure 3: Figure on the left shows the schematic of signal propagation from the pixel to the chip output. Figure on the right illustrates how hit information is encoded within the output waveform, including the address of the RSU (SID), Matrix ID (MID), Unit ID (UID), Pixel ID (PID), and Column ID (CID).
  • Figure 4: First results on the MOST timing: low jitter is observed in the calibration pulse chain (right), at least an order of magnitude lower than the jitter of signals in the readout chain (left).
  • Figure 5: Schematics of the MOST front-end electronics (left) and charge threshold and threshold spread versus VS (right).