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Implementation of Field Programmable Gate Arrays (FPGAs) in Extremely Cold Environments for Space and Cryogenic Computing Applications

Christopher Lewis, Drew Sellers, Michael Hamilton

TL;DR

This paper addresses enabling high-performance CMOS FPGAs to operate in cryogenic space environments typical of cryostats and satellite platforms. It demonstrates the operation of Artix-7 and Zynq Ultrascale+ FPGAs at cryogenic temperatures and presents a comparator-based LDO regulator design to power them locally, reducing heat load from room-temperature supplies. The work documents the testing methodology, performance metrics such as LUT delay and PS/PL power distribution, and shows that 4 K operation is feasible albeit with higher power demands and the need for custom cryogenic boards. The findings indicate a viable path for cryogenic computing and space-readout/control systems, with implications for reduced thermal management and simplified interconnects.

Abstract

The operation of CMOS Field Programmable Gate Arrays (FPGAs) at extremely cold environments as low as 4 K is demonstrated. Various FPGA and periphery hardware design techniques spanning from HDL design to improvements of peripheral circuitry such as discrete voltage regulators are displayed, and their respective performances are reported. While general operating conditions for voltage regulators are widened, FPGAs see a broader temperature range with improved jitter performance, reduced LUT delays, and enhanced transceiver performance at extremely low temperatures.

Implementation of Field Programmable Gate Arrays (FPGAs) in Extremely Cold Environments for Space and Cryogenic Computing Applications

TL;DR

This paper addresses enabling high-performance CMOS FPGAs to operate in cryogenic space environments typical of cryostats and satellite platforms. It demonstrates the operation of Artix-7 and Zynq Ultrascale+ FPGAs at cryogenic temperatures and presents a comparator-based LDO regulator design to power them locally, reducing heat load from room-temperature supplies. The work documents the testing methodology, performance metrics such as LUT delay and PS/PL power distribution, and shows that 4 K operation is feasible albeit with higher power demands and the need for custom cryogenic boards. The findings indicate a viable path for cryogenic computing and space-readout/control systems, with implications for reduced thermal management and simplified interconnects.

Abstract

The operation of CMOS Field Programmable Gate Arrays (FPGAs) at extremely cold environments as low as 4 K is demonstrated. Various FPGA and periphery hardware design techniques spanning from HDL design to improvements of peripheral circuitry such as discrete voltage regulators are displayed, and their respective performances are reported. While general operating conditions for voltage regulators are widened, FPGAs see a broader temperature range with improved jitter performance, reduced LUT delays, and enhanced transceiver performance at extremely low temperatures.

Paper Structure

This paper contains 10 sections, 10 figures, 2 tables.

Table of Contents

  1. Introduction
  2. Hardware Description and Design
  3. FPGA
  4. Improvements to Voltage Regulators
  5. Results
  6. Commercial Evaluation Boards
  7. FPGA Operation and Performance
  8. Low-dropout Regulators
  9. Discussion
  10. Conclusion

Figures (10)

  • Figure 1: Block diagram depicting the external clock, power, and programming sources for interfacing to remote FPGA and LDOs located in dilution refrigerators and/or dunk probes.
  • Figure 2: Photo of the cryogenic assembly housing a Xilinx Artix-7 FPGA with its decoupling network and low dropout voltage regulators.
  • Figure 3: Photo of the cryogenic assembly housing a Xilinx Zynq Ultrascale+ MPSoC with its decoupling network.
  • Figure 4: Circuit diagram of the proposed cryogenic low dropout voltage regulator where $I_L$ is the output load current and $R_1$ and $R_2$ divide the output voltage to a common $V_{ref}$. The filter network for stability consists of $R_3$, $C$, and $R_{esr}$.
  • Figure 5: Plot of the non-inverting input voltage versus output voltage for the (a) TLV271I conventional operational amplifier and for the (b) MCP6541T-E/OT comparator at 77 K with supply voltage (VDD) of 3 V
  • ...and 5 more figures