Mixed Structural Choice Operator: Enhancing Technology Mapping with Heterogeneous Representations

TL;DR

This work tackles the persistent structural bias between logic optimization and technology mapping by introducing Mixed Structural Choices (MCH), a framework that preserves multiple logic representations (e.g., AIG, XAG, XMG) as candidate structures within a mixed choice network and evaluates them using technology costs during mapping. The core contributions include a three-part design: (1) Mixed Structural Choices to maintain diverse representations, (2) an MCH-based technology mapping algorithm that dynamically selects candidate cuts and cells for ASIC and FPGA targets, and (3) extending MCH to mapping-based optimization and graph mapping. Empirical results on EPFL benchmarks demonstrate that MCH-based ASIC and FPGA mappings outperform traditional structural choices and can achieve record-level LUT counts and significant area/delay improvements, while also helping logic optimization escape local optima. The proposed framework offers a scalable, architecture-agnostic approach to heterogeneous synthesis, with practical impact on improving QoR in large-scale designs and providing a robust tool for future mapping-based optimization tasks. In particular, the method formalizes a mapping-aware exploration of multiple representations via parameters such as $k$, $l$, $K$, and $r$, enabling tunable control over cut enumeration, MFFC handling, and path-focused synthesis strategies.

Abstract

The independence of logic optimization and technology mapping poses a significant challenge in achieving high-quality synthesis results. Recent studies have improved optimization outcomes through collaborative optimization of multiple logic representations and have improved structural bias through structural choices. However, these methods still rely on technology-independent optimization and fail to truly resolve structural bias issues. This paper proposes a scalable and efficient framework based on Mixed Structural Choices (MCH). This is a novel heterogeneous mapping method that combines multiple logic representations with technology-aware optimization. MCH flexibly integrates different logic representations and stores candidates for various optimization strategies. By comprehensively evaluating the technology costs of these candidates, it enhances technology mapping and addresses structural bias issues in logic synthesis. Notably, the MCH-based lookup table (LUT) mapping algorithm set new records in the EPFL Best Results Challenge by combining the structural strengths of both And-Inverter Graph (AIG) and XOR-Majority Graph (XMG) logic representations. Additionally, MCH-based ASIC technology mapping achieves a 3.73% area and 8.94% delay reduction (balanced), 20.35% delay reduction (delay-oriented), and 21.02% area reduction (area-oriented), outperforming traditional structural choice methods. Furthermore, MCH-based logic optimization utilizes diverse structures to surpass local optima and achieve better results.

Figures (6)

• Figure 1: Technology mapping for different logic representations
• Figure 2: Comparison of the MCH-based mapping flow with the traditional synthesis flow
• Figure 3: Combine networks to generate a choice network
• Figure 4: Mixed Structural Choices for Technology Mapping Framework
• Figure 5: MCH-based graph mapping