Network-Integrated Decoding System for Real-Time Quantum Error Correction with Lattice Surgery

TL;DR

DecoNet addresses the bottleneck of real-time quantum error correction by distributing decoding across network-integrated FPGA nodes, enabling lattice-surgery-based operations over many logical qubits. It partitions the decoding graph into decoding blocks, uses Fusion Union-Find and parallel window decoding to fuse results across resources, and employs a hybrid tree-grid network to minimize latency. The five-FPGA DecoNet/Helios prototype decodes up to 100 logical qubits at distance $d=5$ with average latency in the microsecond range and throughput well above the measurement rate, demonstrating backlog-free, real-time performance and scalability toward thousands of qubits. This work advances practical fault-tolerant quantum computing by providing a scalable decoding layer that supports dynamic lattice-surgery circuits and inter-qubit interactions across a distributed hardware fabric.

Abstract

Existing real-time decoders for surface codes are limited to isolated logical qubits and do not support logical operations involving multiple logical qubits. We present DECONET, a first-of-its-kind decoding system that scales to thousands of logical qubits and supports logical operations implemented through lattice surgery. DECONET organizes compute resources in a network-integrated hybrid tree-grid structure, which results in minimal latency increase and no throughput degradation as the system grows. Specifically, DECONET can be scaled to any arbitrary number of $l$ logical qubits by increasing the compute resources by $O(l \times log(l))$, which provides the required $O(l)$ growth in I/O resources while incurring only an $O(log(l))$ increase in latency-a modest growth that is sufficient for thousands of logical qubits. Moreover, we analytically show that the scaling approach preserves throughput, keeping DECONET backlog-free for any number of logical qubits. We report an exploratory prototype of DECONET, called DECONET/HELIOS, built with five VMK-180 FPGAs, that successfully decodes 100 logical qubits of distance five. For 100 logical qubits, under a phenomenological noise rate of 0.1%, the DECONET/HELIOS has an average latency of 2.40 μs and an inverse throughput of 0.84 μs per measurement round.

Figures (8)

• Figure 1: Merging of two $d=5$ surface code patches along their $Z_L$ boundaries involves measuring joint ancillas across the boundary to form a single logical patch. Specifically, X-type ancilla qubits connected to two data qubits at the boundary (marked by arrows in the top left) are extended into ancilla qubits interacting with data qubits from both patches (arrows in the top right). Merging also activates previously unused Z-type ancilla qubits at the boundary, whose joint measurement yields the $Z_L Z_L$ operator. The newly activated Z-type ancillas in the merged qubit are shown with red borders.
• Figure 2: Lattice surgery modifies the structure of the decoding graph, assuming under a phenomenological noise model for a $d=5$ surface code. (top) Decoding graph of Z-ancillas over five measurement rounds. (bottom) Decoding graph of a system involving two logical qubits that are merged for five rounds and then split. The decoding graph contains additional vertices (marked in red) when the two logical qubits are merged.
• Figure 3: Timeline of the decoding procedure pipelined across three compute resource groups. Each group performs parallel decoding of its assigned decoding blocks (white boxes). After decoding, DecoNet fuses adjacent decoding blocks in space and time (blue). The system then shares the boundary information between groups (blue arrows). Numbers in the white boxes denote the round index of decoding blocks. Groups 2 and 3 lag behind group 1 due to data dependencies.
• Figure 4: Network Architecture of DecoNet, showing the hybrid tree-grid structure. The tree's leaf nodes run decoder instances, while intermediary nodes route information.
• Figure 5: Internal architecture of DecoNet leaf nodes, comprising a coordinator, router, and multiple decoder instances.