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E-morphic: Scalable Equality Saturation for Structural Exploration in Logic Synthesis

Chen Chen, Guangyu HU, Cunxi Yu, Yuzhe Ma, Hongce Zhang

TL;DR

The paper addresses structural bias in technology mapping by proposing E-morphic, a scalable equality-saturation framework for resynthesis after technology-independent optimization. E-morphic enables parallel structural exploration before mapping, using direct DAG-to-DAG conversion, a simulated annealing-based extraction engine, solution-space pruning, and dual cost models to balance runtime and QoR, with multi-threading and optional ML cost estimation. Empirical results on EPFL large-scale circuits show average improvements of $12.54\%$ in area and $7.29\%$ in delay over a state-of-the-art delay-optimized flow, along with notable runtime efficiency gains when using the ML cost model. The approach demonstrates the practicality of large-scale e-graph-based optimization in logic synthesis and offers integration points with ABC and commercial tools to deliver better post-mapping QoR.

Abstract

In technology mapping, the quality of the final implementation heavily relies on the circuit structure after technology-independent optimization. Recent studies have introduced equality saturation as a novel optimization approach. However, its efficiency remains a hurdle against its wide adoption in logic synthesis. This paper proposes a highly scalable and efficient framework named E-morphic. It is the first work that employs equality saturation for resynthesis after conventional technology-independent logic optimizations, enabling structure exploration before technology mapping. Powered by several key enhancements to the equality saturation framework, such as direct e-graph-circuit conversion, solution-space pruning, and simulated annealing for e-graph extraction, this approach not only improves the scalability and extraction efficiency of e-graph rewriting but also addresses the structural bias issue present in conventional logic synthesis flows through parallel structural exploration and resynthesis. Experiments show that, compared to the state-of-the-art delay optimization flow in ABC, E-morphic on average achieves 12.54% area saving and 7.29% delay reduction on the large-scale circuits in the EPFL benchmark.

E-morphic: Scalable Equality Saturation for Structural Exploration in Logic Synthesis

TL;DR

The paper addresses structural bias in technology mapping by proposing E-morphic, a scalable equality-saturation framework for resynthesis after technology-independent optimization. E-morphic enables parallel structural exploration before mapping, using direct DAG-to-DAG conversion, a simulated annealing-based extraction engine, solution-space pruning, and dual cost models to balance runtime and QoR, with multi-threading and optional ML cost estimation. Empirical results on EPFL large-scale circuits show average improvements of in area and in delay over a state-of-the-art delay-optimized flow, along with notable runtime efficiency gains when using the ML cost model. The approach demonstrates the practicality of large-scale e-graph-based optimization in logic synthesis and offers integration points with ABC and commercial tools to deliver better post-mapping QoR.

Abstract

In technology mapping, the quality of the final implementation heavily relies on the circuit structure after technology-independent optimization. Recent studies have introduced equality saturation as a novel optimization approach. However, its efficiency remains a hurdle against its wide adoption in logic synthesis. This paper proposes a highly scalable and efficient framework named E-morphic. It is the first work that employs equality saturation for resynthesis after conventional technology-independent logic optimizations, enabling structure exploration before technology mapping. Powered by several key enhancements to the equality saturation framework, such as direct e-graph-circuit conversion, solution-space pruning, and simulated annealing for e-graph extraction, this approach not only improves the scalability and extraction efficiency of e-graph rewriting but also addresses the structural bias issue present in conventional logic synthesis flows through parallel structural exploration and resynthesis. Experiments show that, compared to the state-of-the-art delay optimization flow in ABC, E-morphic on average achieves 12.54% area saving and 7.29% delay reduction on the large-scale circuits in the EPFL benchmark.

Paper Structure

This paper contains 21 sections, 9 figures, 3 tables, 1 algorithm.

Table of Contents

  1. Introduction
  2. Background
  3. E-Graph and Equality Saturation
  4. E-Graph Rewriting in Logic Synthesis
  5. Methodology
  6. E-morphic Overview
  7. Efficient Extraction methods
  8. Simulated Annealing e-graph Extraction
  9. Solution Space Pruning for Extraction
  10. Multithreaded Parallel Cost Evaluation
  11. Dual-Model Approach for Cost Estimation
  12. Efficient Implementation
  13. Direct DAG-to-DAG Conversion
  14. Flexible Cost Model Integration
  15. Experiments
  16. ...and 6 more sections

Figures (9)

  • Figure 1: E-morphic: parallel structural exploration for delay finetuning improves the circuit performance.
  • Figure 2: This e-graph represents two equivalent expressions. Each green node is an e-node, and each red-dotted box is an e-class. Edges connect e-nodes to child e-classes.
  • Figure 3: The workflow of E-Synchen2024syn
  • Figure 4: Simulated-annealing-based extraction algorithm.
  • Figure 5: E-morphic overview.
  • ...and 4 more figures