Design and Verification of a Synchronus First In First Out (FIFO)
Yatheeswar Penta, Riadul Islam
TL;DR
This work addresses the design and verification of a synchronous FIFO suitable for single-clock-domain data buffering. It presents a Verilog RTL implementation (8 entries, 8-bit width) and a comprehensive verification strategy combining UVM-based testbenches, traditional Verilog testing, and FPGA hardware testing. The key contributions include a structured UVM environment with dedicated Sequence, Sequencer, Driver, Monitor, Scoreboard, Agent, and Environment components, plus hardware validation on an Intel Cyclone V board to confirm timing and data integrity. The results demonstrate correct data transfer, accurate full/empty flag behavior, and reliable timing synchronization, highlighting the approach's practicality for high-speed buffering and clock-domain management in modern digital systems.
Abstract
This project focuses on designing and verifying a synchronous FIFO First In First Out (FIFO) memory, a critical component in digital systems for temporary data storage and seamless data transfer. The FIFO operates under a single clock domain, ensuring synchronized read and write operations, making it suitable for systems requiring high-speed, reliable data buffering. This design includes FIFO's key features, such as read and write operations, full and empty flag generation, and pointer management for memory control. The FIFO was implemented using Verilog to define the Register Transfer Level (RTL) design, ensuring functionality and timing requirements were met. For verification, three approaches were employed: (1) UVM-based Verification: A Universal Verification Methodology (UVM) testbench was developed to test the FIFO design rigorously. The testbench includes components like interface, sequence item, driver, monitor, scoreboard, agent, and environment. Directed and random tests were performed to verify corner cases, such as simultaneous reads and writes, full and empty conditions, and overflow and underflow scenarios; (2) Traditional Verilog Testbench: A standalone Verilog testbench was also used to validate the functionality of the FIFO through directed test scenarios and waveform analysis; (3) FPGA implementation: Additionally, the design was implemented on an FPGA for real-time testing to verify its functionality and timing behavior in hardware. FPGA-based verification ensured the design performed as expected under practical conditions. The results confirmed the correct operation of the FIFO, including accurate data transfer, flag behavior, and timing synchronization. The project successfully demonstrated the robustness and reliability of the synchronous FIFO design, highlighting its importance in modern digital systems for efficient data handling and buffering.