A 10.8mW Mixed-Signal Simulated Bifurcation Ising Solver using SRAM Compute-In-Memory with 0.6us Time-to-Solution

TL;DR

This work presents a CMOS-based mixed-signal simulated bifurcation Ising solver that leverages SRAM compute-in-memory and on-chip decaying noise to solve NP-hard COPs, notably MAXCUT, with high speed and energy efficiency. A 10-T SRAM macro enables ternary multiplication, while a synchronous SB loop using analog noise accelerates convergence on all-to-all connected graphs. Key results show sub-microsecond time-to-solution ($0.6\,\mu s$) and low average power ($10.8\,\mathrm{mW}$) for 60-node problems, surpassing prior CMOS and other implementations. The approach offers robust edge-ready performance and scalability potential, with future work aimed at multi-bit weights and larger problem sizes on advanced processes, enabling applications such as massive MIMO detection.

Abstract

Combinatorial optimization problems are funda- mental for various fields ranging from finance to wireless net- works. This work presents a simulated bifurcation (SB) Ising solver in CMOS for NP-hard optimization problems. Analog domain computing led to a superior implementation of this algorithm as inherent and injected noise is required in SB Ising solvers. The architecture novelties include the use of SRAM compute-in-memory (CIM) to accelerate bifurcation as well as the generation and injection of optimal decaying noise in the analog domain. We propose a novel 10-T SRAM cell capable of performing ternary multiplication. When measured with 60- node, 50% density, random, binary MAXCUT graphs, this all- to-all connected Ising solver reliably achieves above 93% of the ground state solution in 0.6us with 10.8mW average power in TSMC 180nm CMOS. Our chip achieves an order of magnitude improvement in time-to-solution and power compared to previously proposed Ising solvers in CMOS and other platforms.

Figures (10)

• Figure 1: Concept of a binary-weighted MAXCUT problem and the proposed simulated bifurcation (SB) Ising machine.
• Figure 2: Proposed mixed-signal architecture with custom cells for SB Ising-CIM and analog noise injection.
• Figure 3: Circuit implementation and SB operation mode of proposed coupling cell (left), custom self-feedback cell (top right), and custom current-domain noise injection cell (bottom right).
• Figure 4: Low-frequency circuit measurements of 10-T cell transient behavior.
• Figure 5: Noise generation DAC for on-chip noise injection.