LoopLynx: A Scalable Dataflow Architecture for Efficient LLM Inference

TL;DR

LoopLynx introduces a hybrid spatial-temporal dataflow architecture to accelerate LLM inference on FPGAs and scales to multi-FPGA deployments. It employs macro dataflow kernels, such as fused matrix processing and fused multi-head attention, coordinated by a scheduler over a ring interconnect to hide data transfer latency and improve hardware utilization. In GPT-2 experiments, LoopLynx achieves up to 2.52x speed-up over Nvidia A100 with dual-FPGA configurations while consuming roughly half the energy, and maintains favorable comparisons against single-FPGA baselines. These results demonstrate the practicality of FPGA-based LLM serving, particularly for long-context generation tasks, by leveraging hybrid scheduling and large dataflow kernels to maximize throughput and energy efficiency.

Abstract

In this paper, we propose LoopLynx, a scalable dataflow architecture for efficient LLM inference that optimizes FPGA usage through a hybrid spatial-temporal design. The design of LoopLynx incorporates a hybrid temporal-spatial architecture, where computationally intensive operators are implemented as large dataflow kernels. This achieves high throughput similar to spatial architecture, and organizing and reusing these kernels in a temporal way together enhances FPGA peak performance. Furthermore, to overcome the resource limitations of a single device, we provide a multi-FPGA distributed architecture that overlaps and hides all data transfers so that the distributed accelerators are fully utilized. By doing so, LoopLynx can be effectively scaled to multiple devices to further explore model parallelism for large-scale LLM inference. Evaluation of GPT-2 model demonstrates that LoopLynx can achieve comparable performance to state-of-the-art single FPGA-based accelerations. In addition, compared to Nvidia A100, our accelerator with a dual-FPGA configuration delivers a 2.52x speed-up in inference latency while consuming only 48.1% of the energy.

Figures (8)

• Figure 1: Illustration of 2-stages of LLM inference
• Figure 2: The overall architecture of LoopLynx. Accelerators are connected via a ring network and operating under model parallel scheme.
• Figure 3: LLM inference under different architectures: (a) execution of temporal architecture. (b) execution of spatial architecture. (c) execution of our proposed hybrid spatial-temporal architecture.
• Figure 4: Latency optimization techniques.
• Figure 5: Latency Breakdown of 1-node on GPT-2 and improvement over different optimization techniques.