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A Fully Planar Approach to Field-coupled Nanocomputing: Scalable Placement and Routing Without Wire Crossings

Benjamin Hien, Marcel Walter, Simon Hofmann, Robert Wille

TL;DR

This work tackles the practical barrier of wire crossings in Field-Coupled Nanocomputing (FCN) by introducing a fully planar design flow and a scalable planarity-preserving P&R algorithm. The approach planarizes the logic network, preserves planarity through a 2DDWave clocking scheme, and employs gap-based placement to confine routing to adjacent levels, achieving crossing-free FCN layouts. Evaluation demonstrates scalability to circuits with up to $149{,}000$ gates, reaching $182\times$ larger complexity than prior planar methods, with rapid P&R performance and meaningful area improvements after post-layout optimization. The results establish a pathway for large-scale FCN deployment on a single fabrication layer, mitigating reliability concerns associated with wire crossings and enhancing practical viability.

Abstract

Field-coupled Nanocomputing (FCN) is a class of promising post-CMOS technologies that transmit information through electric or magnetic fields instead of current flow. They utilize basic building blocks called cells, which can form gates that implement Boolean functions. However, the design constraints for FCN circuits differ significantly from those for CMOS. One major challenge is that wires in FCN have to be realized as gates, i.e., they are constructed from cells and incur the same costs as gates. Additionally, all FCN technologies are fabricated on a single layer, e.g., a silicon surface, requiring all elements -- gates and wires -- to be placed within that same layer. Consequently, FCN employs special gates, called wire crossings, to enable signals to cross. While existing wire-crossing implementations are complex and were previously considered costly, initial efforts have aimed at minimizing their use. However, recent physical simulations and experiments on a quantum annealing platform have shown that currently used wire crossings in FCN significantly compromise signal stability, to the extent that circuits cannot function reliably. This work addresses that issue by introducing the first placement and routing algorithm that produces fully planar FCN circuits, eliminating the need for all wire crossings. For a comparative evaluation, a state-of-the-art placement and routing algorithm was also modified to enforce planarity. However, our proposed algorithm is more scalable and can handle inputs with up to 149k gates, enabling it to process circuits that are 182x more complex than those handled by the modified state-of-the-art algorithm.

A Fully Planar Approach to Field-coupled Nanocomputing: Scalable Placement and Routing Without Wire Crossings

TL;DR

This work tackles the practical barrier of wire crossings in Field-Coupled Nanocomputing (FCN) by introducing a fully planar design flow and a scalable planarity-preserving P&R algorithm. The approach planarizes the logic network, preserves planarity through a 2DDWave clocking scheme, and employs gap-based placement to confine routing to adjacent levels, achieving crossing-free FCN layouts. Evaluation demonstrates scalability to circuits with up to gates, reaching larger complexity than prior planar methods, with rapid P&R performance and meaningful area improvements after post-layout optimization. The results establish a pathway for large-scale FCN deployment on a single fabrication layer, mitigating reliability concerns associated with wire crossings and enhancing practical viability.

Abstract

Field-coupled Nanocomputing (FCN) is a class of promising post-CMOS technologies that transmit information through electric or magnetic fields instead of current flow. They utilize basic building blocks called cells, which can form gates that implement Boolean functions. However, the design constraints for FCN circuits differ significantly from those for CMOS. One major challenge is that wires in FCN have to be realized as gates, i.e., they are constructed from cells and incur the same costs as gates. Additionally, all FCN technologies are fabricated on a single layer, e.g., a silicon surface, requiring all elements -- gates and wires -- to be placed within that same layer. Consequently, FCN employs special gates, called wire crossings, to enable signals to cross. While existing wire-crossing implementations are complex and were previously considered costly, initial efforts have aimed at minimizing their use. However, recent physical simulations and experiments on a quantum annealing platform have shown that currently used wire crossings in FCN significantly compromise signal stability, to the extent that circuits cannot function reliably. This work addresses that issue by introducing the first placement and routing algorithm that produces fully planar FCN circuits, eliminating the need for all wire crossings. For a comparative evaluation, a state-of-the-art placement and routing algorithm was also modified to enforce planarity. However, our proposed algorithm is more scalable and can handle inputs with up to 149k gates, enabling it to process circuits that are 182x more complex than those handled by the modified state-of-the-art algorithm.

Paper Structure

This paper contains 12 sections, 7 figures, 1 table.

Figures (7)

  • Figure 1: FCN technology implementations.
  • Figure 2: QCA ONE reis2016methodology gate implementations of an (a) Inverter, (b) wire, (c) fan-out, (d) 3D- and (e) co-planar wire crossing.
  • Figure 3: Common clocking schemes for FCN circuit layouts.
  • Figure 4: Proposed design flow for fully planar FCN circuit layouts, starting from a high-level description and eventually yielding a cell-level layout of a specific technology.
  • Figure 5: Logic network planarization through balancing and node duplication.
  • ...and 2 more figures

Theorems & Definitions (4)

  • Example 1
  • Example 2
  • Example 3
  • Example 4