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AC-LGADs Fermilab Front-End Electronics Characterization

René Ríos, Esteban Felipe Molina Cardenas, Cristian Peña, Orlando Soto, William Brooks, Artur Apresyan, Sergey Los, Claudio San Martín

TL;DR

The paper characterizes Fermilab's AC-LGAD front-end electronics (FEE) to quantify how the readout chain affects timing resolution for high-rate LGAD detectors. Using a 16-channel DUT, a MIP-mimicking pulse setup, and comprehensive measurements of gain, jitter, frequency response, and noise, the authors fit a jitter model that links timing precision to signal-to-noise ratio and rise time. They report an asymptotic jitter floor of about $\delta t \approx 4.23$ ps and, after accounting for the pulse-generator contribution, an upper limit on the FEE timing contribution of $\sigma_{\text{FEE}} \lesssim 2$ ps at $1\sigma$, indicating the FEE can preserve sub-ps timing information. The findings validate that high-gain, low-noise amplification with adequate bandwidth is essential to reach the desired timing performance for AC-LGADs and inform future multi-channel readout designs for high-luminosity experiments.

Abstract

We characterized the front-end electronics used to process high-frequency signals from low-gain avalanche diodes (LGADs) at the Fermilab Test Beam Facility. LGADs are silicon detectors employed for charged particle tracking, offering exceptional spatial and temporal resolution. The purpose of this characterization was to understand how the time resolution is influenced by the front-end electronics. To achieve this, we developed a setup capable of generating input signals with varying amplitudes. The output results demonstrated that signal processing by the front-end electronics plays a crucial role in enhancing time resolution. We showed that the time resolution achieved by the FEE board is better than $2\: ps$ at the $1σ$ level.

AC-LGADs Fermilab Front-End Electronics Characterization

TL;DR

The paper characterizes Fermilab's AC-LGAD front-end electronics (FEE) to quantify how the readout chain affects timing resolution for high-rate LGAD detectors. Using a 16-channel DUT, a MIP-mimicking pulse setup, and comprehensive measurements of gain, jitter, frequency response, and noise, the authors fit a jitter model that links timing precision to signal-to-noise ratio and rise time. They report an asymptotic jitter floor of about ps and, after accounting for the pulse-generator contribution, an upper limit on the FEE timing contribution of ps at , indicating the FEE can preserve sub-ps timing information. The findings validate that high-gain, low-noise amplification with adequate bandwidth is essential to reach the desired timing performance for AC-LGADs and inform future multi-channel readout designs for high-luminosity experiments.

Abstract

We characterized the front-end electronics used to process high-frequency signals from low-gain avalanche diodes (LGADs) at the Fermilab Test Beam Facility. LGADs are silicon detectors employed for charged particle tracking, offering exceptional spatial and temporal resolution. The purpose of this characterization was to understand how the time resolution is influenced by the front-end electronics. To achieve this, we developed a setup capable of generating input signals with varying amplitudes. The output results demonstrated that signal processing by the front-end electronics plays a crucial role in enhancing time resolution. We showed that the time resolution achieved by the FEE board is better than at the level.

Paper Structure

This paper contains 20 sections, 8 equations, 14 figures, 2 tables.

Table of Contents

  1. Introduction
  2. AC-LGADs Fermilab Front-End Electronics
  3. Experimental Setup Overview
  4. Gain and Jitter characterization
  5. Experimental Setup
  6. Overview of The Pulses
  7. Gain Results
  8. Jitter measurement
  9. Time resolution
  10. Pulse generator and associated electronics jitter
  11. Output amplitudes, rise time, jitter, noise and SNR
  12. FEE Board Time Resolution
  13. Frequency Response
  14. Experimental Setup
  15. Results
  16. ...and 5 more sections

Figures (14)

  • Figure 1: FEE board (a) with the designed charge injector (b) in place of an AC-LGAD.
  • Figure 2: Single channel equivalent schematic.
  • Figure 3: From left to right: clock generator (a), oscilloscope (b), power supply (c), pulse generator (d), EMI shielded enclosure containing the DUT (e), and multimeter for RTD measurement (f).
  • Figure 4: Output from the pulse generator without any attenuation applied.
  • Figure 5: Experimental setup for amplitude, noise RMS and jitter analysis.
  • ...and 9 more figures