ML For Hardware Design Interpretability: Challenges and Opportunities

TL;DR

This paper analyzes how large language models can enhance design interpretability by generating natural language descriptions for RTL code (RTL-to-NL), a key bottleneck in hardware design. It surveys current LLM-based efforts (e.g., DeepRTL, SpecLLM, ChipNeMo) and contrasts RTL-to-NL with NL-to-RTL tasks, highlighting infrastructure gaps in datasets, evaluation benchmarks, and learning frameworks. The authors identify concrete challenges—dataset scarcity, long-context processing, and domain-specific semantics—and propose research opportunities in dataset construction, novel evaluation methods, long-context architectures, and LLM-aware EDA tooling. The work argues that improving RTL-to-NL can materially speed up the hardware design cycle, enable better integration of IP, and help align AI-assisted design processes with human engineers. Overall, the paper lays a roadmap for leveraging ML to automate design interpretability tasks and accelerate the production of custom hardware accelerators for ML workloads and beyond.

Abstract

The increasing size and complexity of machine learning (ML) models have driven the growing need for custom hardware accelerators capable of efficiently supporting ML workloads. However, the design of such accelerators remains a time-consuming process, heavily relying on engineers to manually ensure design interpretability through clear documentation and effective communication. Recent advances in large language models (LLMs) offer a promising opportunity to automate these design interpretability tasks, particularly the generation of natural language descriptions for register-transfer level (RTL) code, what we refer to as "RTL-to-NL tasks." In this paper, we examine how design interpretability, particularly in RTL-to-NL tasks, influences the efficiency of the hardware design process. We review existing work adapting LLMs for these tasks, highlight key challenges that remain unaddressed, including those related to data, computation, and model development, and identify opportunities to address them. By doing so, we aim to guide future research in leveraging ML to automate RTL-to-NL tasks and improve hardware design interpretability, thereby accelerating the hardware design process and meeting the increasing demand for custom hardware accelerators in machine learning and beyond.

Figures (4)

• Figure 1: The standard VLSI design flow consists of a front-end phase, where functionality is specified, implemented in RTL, and verified, followed by a back-end phase, where the design undergoes synthesis, physical design, and final preparation for fabrication.
• Figure 2: An example of a possible RTL-to-NL task, where the goal is to generate natural language documentation for an RTL design described in Verilog.
• Figure 3: An example of how hand-written Verilog may compare to the code generated by High-Level Synthesis tools. The HLS-generated code in the figure was generated by Bambu HLS bambu as well as Catapult HLS catapult_hls.
• Figure 4: We asked GPT4o-mini to evaluate the critical path of simple Verilog modules. This figure shows how the model will give incorrect or inconsistent answers. For this example, the path leading to f will have a longer critical path due to carry logic necessary for the adders.