High-Level Synthesis using SDF-AP, Template Haskell, QuasiQuotes, and GADTs to Generate Circuits from Hierarchical Input Specification

TL;DR

This work advances high-level synthesis for FPGAs by introducing hierarchical pattern specifications in a functional framework based on SDF-AP, Template Haskell, and GADTs. By coupling automatic data/control path generation with parameterized, reusable buffers and HoF-driven patterns, the approach yields transparent resource scheduling and scalable parallelism, validated against Vitis HLS using Clash's interactive environment and a golden-model for verification. The methodology enables compositional reuse of subcomponents, automated graph extraction from annotated specifications, and a flow that combines synthesis, simulation, and testing with predictable resource implications. Case studies on multi-dimensional maps and center-of-mass computations demonstrate strong scheduling control and improved predictability, suggesting meaningful practical impact for developing FPGA accelerators with explicit parallelism and hierarchy.

Abstract

FPGAs provide highly parallel and customizable hardware solutions but are traditionally programmed using low-level Hardware Description Languages (HDLs) like VHDL and Verilog. These languages have a low level of abstraction and require engineers to manage control and scheduling manually. High-Level Synthesis (HLS) tools attempt to lift this level of abstraction by translating C/C++ code into hardware descriptions, but their reliance on imperative paradigms leads to challenges in deriving parallelism due to pointer aliasing and sequential execution models. Functional programming, with its inherent purity, immutability, and parallelism, presents a more natural abstraction for FPGA design. Existing functional hardware description tools such as Clash enable high-level circuit descriptions but lack automated scheduling and control mechanisms. Prior work by Folmer introduced a framework integrating SDF-AP graphs into Haskell for automatic hardware generation, but it lacked hierarchy and reusability. This paper extends that framework by introducing hierarchical pattern specification, enabling structured composition and scalable parallelism. Key contributions include: (1) automatic hardware generation, where both data and control paths are derived from functional specifications with hierarchical patterns, (2) parameterized buffers using GADTs, eliminating the need for manual buffer definitions and facilitating component reuse, and (3) provision of a reference "golden model" that can be simulated in the integrated environment for validation. The core focus of this paper is on methodology. But we also evaluate our approach against Vitis HLS, comparing both notation and resulting hardware architectures. Experimental results demonstrate that our method provides greater transparency in resource utilization and scheduling, often outperforming Vitis in both scheduling and predictability.

Figures (7)

• Figure 1: Conformance relation code, graph, and hardware
• Figure 2: Hierarchical structure of composed hardware.
• Figure 3: Composition of f and g
• Figure 4: graphs of s
• Figure 5: 3-dimensional s with patterns