High-Level Synthesis of Digital Circuits from Template Haskell and SDF-AP
Hendrik Folmer, Robert de Groote, Marco Bekooij
TL;DR
The paper tackles the lack of temporal semantics in functional hardware specifications used by High-Level Synthesis. It introduces SDF-AP patterns to encode timing and resource constraints and builds a tool flow based on Template Haskell and the Clash compiler to generate clocked RTL. Experiments with dot-product, Center of Mass, and 2D DCT show consistent timing and resource behavior and demonstrate competitive performance versus Vitis and Intel HLS, often with transparency advantages. The work enables more predictable time-area trade-offs and a more transparent design process, enabling iterative development with strong correctness guarantees.
Abstract
Functional languages as input specifications for High-Level Synthesis (HLS) tools allow to specify data dependencies but do not contain a notion of time nor execution order. In this paper, we propose a method to add this notion to the functional description using the dataflow model SDF-AP. SDF-AP consists of patterns that express consumption and production that we can use to enforce resource usage. We created an HLS-tool that can synthesize parallel hardware, both data and control path, based on the repetition, expressed in Higher-Order Functions, combined with specified SDF-AP patterns. Our HLS-tool, based on Template Haskell, generates an Abstract Syntax Tree based on the given patterns and the functional description uses the Clash-compiler to generate VHDL/Verilog. Case studies show consistent resource consumption and temporal behavior for our HLS. A comparison with a commercially available HLS-tool shows that our HLS tool outperforms in terms of latency and sometimes in resource consumption. The method and tool presented in this paper offer more transparency to the developer and allow to specify more accurately the synthesized hardware compared to what is possible with pragmas of the Vitis HLS-tool.