Accelerating Hybrid XOR$-$CNF SAT Problems Natively with In-Memory Computing
Haesol Im, Fabian Böhm, Giacomo Pedretti, Noriyuki Kushida, Moslem Noori, Elisabetta Valiante, Xiangyi Zhang, Chan-Woo Yang, Tinish Bhattacharya, Xia Sheng, Jim Ignowski, Arne Heittmann, John Paul Strachan, Masoud Mohseni, Ray Beausoleil, Thomas Van Vaerenbergh, Ignacio Rozada
TL;DR
The work tackles the challenge of efficiently solving hybrid XOR--CNF SAT problems by proposing a native XOR--CNF solver implemented on in-memory computing hardware. It introduces WalkSAT-XNF, a full-neighborhood gradient-based local search that operates directly on XNF representations, and an IMC accelerator architecture using memristor crossbars to evaluate CNF and XOR clauses in parallel. Experimental demonstrations with TaO$_x$ memristors and 28-nm simulations show significant improvements: up to roughly 10× faster and up to 1000× more energy-efficient than CPU-based solvers, with a substantial chip-area reduction when using XNF. The results indicate strong potential for energy-efficient, high-throughput hardware solvers for cryptographic and industrial SAT problems, and point to scalable paths via multi-tile crossbar deployments and integrated preprocessing strategies.
Abstract
The Boolean satisfiability (SAT) problem is a computationally challenging decision problem central to many industrial applications. For SAT problems in cryptanalysis, circuit design, and telecommunication, solutions can often be found more efficiently by representing them with a combination of exclusive OR (XOR) and conjunctive normal form (CNF) clauses. We propose a hardware accelerator architecture that natively embeds and solves such hybrid CNF$-$XOR problems using in-memory computing hardware. To achieve this, we introduce an algorithm and demonstrate, both experimentally and through simulations, how it can be efficiently implemented with memristor crossbar arrays. Compared to the conventional approaches that translate CNF$-$XOR problems to pure CNF problems, our simulations show that the accelerator improves computation speed, energy efficiency, and chip area utilization by $\sim$10$\times$ for a set of hard cryptographic benchmarking problems. Moreover, the accelerator achieves a $\sim$10$\times$ speedup and a $\sim$1000$\times$ gain in energy efficiency over state-of-the-art SAT solvers running on CPUs.
