Logo
ScienceStack
Table of Contents
Fetching ...
Sign In

FERIVer: An FPGA-assisted Emulated Framework for RTL Verification of RISC-V Processors

Kun Qin, Xiaorang Guo, Martin Schulz, Carsten Trinitis

TL;DR

The paper tackles the verification bottleneck in RISCV processors arising from the speed–accuracy trade-off between ISA simulations and hardware emulation. It introduces FERIVer, an FPGA-assisted SoC framework that runs a function-accurate ISS on the host CPU and a RTL RISCV core on the FPGA fabric, coordinating via an Arbiter, PCAP Bridge, and a Re-constructor to perform real-time cross-verification. Key contributions include a detailed top-level architecture with a practical workflow, a PCAP-based RTL observation approach, and a reconstruction pipeline that renders checkpoints and waveforms for debugging. Empirical results show FERIVer delivering up to 5.31 MIPS and substantial speedups (20x–35x vs Verilator, 150x–177x vs XSim) with low PL resource usage, enabling rapid exploration of RISCV ISA variants and extensions.

Abstract

Processor design and verification require a synergistic approach that combines instruction-level functional simulations with precise hardware emulations. The trade-off between speed and accuracy in the instruction set simulation poses a significant challenge to the efficiency of processor verification. By tapping the potentials of Field Programmable Gate Arrays (FPGAs), we propose an FPGA-assisted System-on-Chip (SoC) platform that facilitates cross-verification by the embedded CPU and the synthesized hardware in the programmable fabrics. This method accelerates the verification of the RISC-V Instruction Set Architecture (ISA) processor at a speed of 5 million instructions per second (MIPS), which is 150x faster than the vendor-specific tool (Xilinx XSim) and a 35x boost to the state-of-the-art open-source verification setup (Verilator). With less than 7\% hardware occupation on Zynq 7000 FPGA, the proposed framework enables flexible verification with high time and cost efficiency for exploring RISC-V instruction set architectures.

FERIVer: An FPGA-assisted Emulated Framework for RTL Verification of RISC-V Processors

TL;DR

The paper tackles the verification bottleneck in RISCV processors arising from the speed–accuracy trade-off between ISA simulations and hardware emulation. It introduces FERIVer, an FPGA-assisted SoC framework that runs a function-accurate ISS on the host CPU and a RTL RISCV core on the FPGA fabric, coordinating via an Arbiter, PCAP Bridge, and a Re-constructor to perform real-time cross-verification. Key contributions include a detailed top-level architecture with a practical workflow, a PCAP-based RTL observation approach, and a reconstruction pipeline that renders checkpoints and waveforms for debugging. Empirical results show FERIVer delivering up to 5.31 MIPS and substantial speedups (20x–35x vs Verilator, 150x–177x vs XSim) with low PL resource usage, enabling rapid exploration of RISCV ISA variants and extensions.

Abstract

Processor design and verification require a synergistic approach that combines instruction-level functional simulations with precise hardware emulations. The trade-off between speed and accuracy in the instruction set simulation poses a significant challenge to the efficiency of processor verification. By tapping the potentials of Field Programmable Gate Arrays (FPGAs), we propose an FPGA-assisted System-on-Chip (SoC) platform that facilitates cross-verification by the embedded CPU and the synthesized hardware in the programmable fabrics. This method accelerates the verification of the RISC-V Instruction Set Architecture (ISA) processor at a speed of 5 million instructions per second (MIPS), which is 150x faster than the vendor-specific tool (Xilinx XSim) and a 35x boost to the state-of-the-art open-source verification setup (Verilator). With less than 7\% hardware occupation on Zynq 7000 FPGA, the proposed framework enables flexible verification with high time and cost efficiency for exploring RISC-V instruction set architectures.

Paper Structure

This paper contains 19 sections, 7 figures, 2 tables.

Table of Contents

  1. Introduction
  2. Background
  3. Open-source Software-based Processor Simulator
  4. Verification on Heterogeneous FPGA SoC
  5. Manually Created RTL Signal Probes
  6. Signal Analyzer IP
  7. Bitstream Readback
  8. FERIVer Framework
  9. Top-level Architecture
  10. Arbiter (block ① in Figure \ref{['blockdiagram']})
  11. PCAP Bridge (block ② in Figure \ref{['blockdiagram']})
  12. Re-constructor (block ③ in Figure \ref{['blockdiagram']})
  13. Typical Workflow
  14. Mechanism of the Verification Acceleration
  15. Evaluation and Discussion
  16. ...and 4 more sections

Figures (7)

  • Figure 1: Block diagram of the system-level architecture.
  • Figure 2: An Arbiter is designed for PCAP initialization and mismatch checking .
  • Figure 3: Data path and control path of PL readback via PCAP bridge.
  • Figure 4: Typical workflow of FERIVer. The co-verification procedure is divided into 5 stages and processed in 3 domains.
  • Figure 5: An illustrative comparison between conventional verification tools and the FERIVer method (absolute processing time, shorter is better). The example scenario presents the execution of 5 consecutive instructions, where the ISS employs an RV32I abstraction layer and works as a reference model, and the DUT entity fails on the execution of the 4th instruction.
  • ...and 2 more figures