All-to-all connectivity of Rydberg-atom-based quantum processors with messenger qubits

TL;DR

The paper tackles the connectivity bottleneck in neutral-atom quantum processors by introducing messenger qubits that move between static computational qubits to enable all-to-all interactions. It proposes five architectures—two-way and one-way conveyor belts, throw-catch-throw, shuttle-and-route, and throw-and-measure—each with distinct trade-offs in gate count, shuttling, and readout requirements, and provides unified fidelity and gate-time analyses. The discussion contrasts these messenger-based schemes with reconfigurable Rydberg arrays, highlighting that messenger qubits can decouple circuit depth from size while introducing transport-related errors and engineering challenges. The work identifies key technological components and focusing on multi-species layouts, native SWAP gates, and fast mid-circuit readout as essential avenues, suggesting that near- to mid-term progress could yield scalable, fully connected neutral-atom quantum processors if these hurdles are overcome.

Abstract

Rydberg atom arrays are a front-running platform for quantum processors. A major challenge threatening the scalability of this platform is the limited qubit connectivity due to the finite range of interatomic interactions. We explore an approach to realize dynamical all-to-all connectivity with the use of moving "messenger" atomic qubits that couple distant "computational" qubits held in a static tweezer array. We detail and compare four specific architectures based on this concept, each presenting distinct advantages and challenges tied to the efficacy of techniques used to couple, move and measure atomic qubits. We demonstrate that, though technologically demanding, the messenger-qubit paradigm opens a promising avenue to a truly scalable quantum processor based on Rydberg atoms.

Figures (8)

• Figure 1: A straightforward way to perform a logic gate between two distant target qubits, $A$ and $B$, is to perform a sequence of physical gates between neighbouring qubits along some path. The drawback of this approach is the growth of the physical gate count per a logic gate with the processor size and, as a consequence, the exponential drop of the logic gate fidelity with the number of qubits.
• Figure 2: Two-way conveyor belt architecture. Upper row: general layout. Computational qubits (shown in orange) reside at rest in an immobile tweezer array in the computational zone. Messenger qubits (shown in blue or green, depending on the direction of movement) are shuttleged by atomic conveyor belts realized by moving tweezer arrays. There are four conveyor belts: two of them move in the opposite horizontal directions (shown in blue) and two -- in the opposite vertical directions. The messenger qubits are dynamically loaded to the conveyor belts from reservoirs in the loading zones. Lower row: a sequence of physical nearest-neighbor two-qubit gates implementing a logical two-qubit gate between target computational qubits, A and B, located in the opposite corners of the array. The physical two-qubit gates are shown by dashed black ellipses and enumerated in the order of execution. In total, four messenger qubits from four different conveyor belts are employed to entangle two target computational qubits.
• Figure 3: One-way conveyor belt architecture. Upper row: general layout. Analogously to the two-way conveyor belt architecture shown in Fig. \ref{['fig:two-way']}, messenger qubits are shuttleged by atomic conveyor belts moving with constant velocities. However, here there are only two conveyor belts (and two loading zones) instead of four. The reverse flow of information is accomplished by a quantum teleportation protocol involving measurements over messenger qubits and conditional single-qubit gates over computational qubits. Measurements are performed in two readout zones. Middle and lower row: two sequences of physical gates and measurements implementing a logical two-qubit gate between target computational qubits for two nonequivalent relative locations of target qubits. The physical two-qubit gates, single-qubit gates and single-qubit measurements are shown by dashed black ellipses, black squares and red squares, respectively. The measurements are performed in the basis $\ket{\pm} = \left(\ket{0}\pm\ket{1}\right)/\sqrt{2}$.
• Figure 4: Throw-catch-throw architecture. Upper row: general layout. A messenger qubit is launched by purpose-built optical tweezers operating within the throw zone and flies freely through the computational zone. Its trajectory passes by two target computational qubits, A and B. Two two-qubit gates are performed between the messenger and each of the target computational qubits during this passage. Then the messenger qubit enters the catch-and-throw zone, where it is decelerated ("caught") and re-launched towards the target computational qubit A by catch-and-through tweezers Hwang_2023_Optical. The third two-qubit gate is performed between the messenger qubit and computational qubit A during the backwards passage. Lower row: A sequence of physical gates implementing a logical two-qubit gate between target computational qubits.
• Figure 5: Shuttle-and-route architecture. A single messenger qubit is used to implement a logical qubit gate between computational qubits A and B. This messenger qubit is shuttled by conveyor belts through the computational zone and transferred from one conveyor belt to another, orthogonal one, outside the computational zone. A sequence of physical gates implementing a logical two-qubit gate between target computational qubits is identical to that for the throw-catch-throw architecture, cf. Fig. \ref{['fig:throw-catch-throw']}.