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Virtual memory for real-time systems using hPMP

Konrad Walluszik, Daniel Auge, Gerhard Wirrer, Holm Rauchfuss, Thomas Roecker

TL;DR

The paper tackles the challenge of providing memory protection for automotive real-time systems without sacrificing deterministic timing. It extends the RISC-V SPMP framework with a hypervisor-controlled hpmp extension that enables address redirection via per-region offsets, allowing guest code to use guest-physical addresses while the hypervisor maps them to physical addresses through $PA = GPA + hpmpoffset_{<x>}$ with $x = 2k + 1$. The approach maintains an OFF-TOR translation model and supports scenarios such as partial updates and generic VM images, enabling VM switching via hpmpswitch. This yields virtual memory capabilities suitable for real-time automotive controllers, reducing hardware costs while preserving isolation and timing predictability. The work outlines future evaluation of corner cases, area/power/timing feasibility, and integration challenges with the hypervisor, indicating a practical path toward real-time virtualized automotive systems.

Abstract

To satisfy automotive safety and security requirements, memory protection mechanisms are an essential component of automotive microcontrollers. In today's available systems, either a fully physical address-based protection is implemented utilizing a memory protection unit, or a memory management unit takes care of memory protection while also mapping virtual addresses to physical addresses. The possibility to develop software using a large virtual address space, which is agnostic to the underlying physical address space, allows for easier software development and integration, especially in the context of virtualization. In this work, we showcase an extension to the current RISC-V SPMP proposal that enables address redirection for selected address regions, while maintaining the fully deterministic behavior of a memory protection unit.

Virtual memory for real-time systems using hPMP

TL;DR

The paper tackles the challenge of providing memory protection for automotive real-time systems without sacrificing deterministic timing. It extends the RISC-V SPMP framework with a hypervisor-controlled hpmp extension that enables address redirection via per-region offsets, allowing guest code to use guest-physical addresses while the hypervisor maps them to physical addresses through with . The approach maintains an OFF-TOR translation model and supports scenarios such as partial updates and generic VM images, enabling VM switching via hpmpswitch. This yields virtual memory capabilities suitable for real-time automotive controllers, reducing hardware costs while preserving isolation and timing predictability. The work outlines future evaluation of corner cases, area/power/timing feasibility, and integration challenges with the hypervisor, indicating a practical path toward real-time virtualized automotive systems.

Abstract

To satisfy automotive safety and security requirements, memory protection mechanisms are an essential component of automotive microcontrollers. In today's available systems, either a fully physical address-based protection is implemented utilizing a memory protection unit, or a memory management unit takes care of memory protection while also mapping virtual addresses to physical addresses. The possibility to develop software using a large virtual address space, which is agnostic to the underlying physical address space, allows for easier software development and integration, especially in the context of virtualization. In this work, we showcase an extension to the current RISC-V SPMP proposal that enables address redirection for selected address regions, while maintaining the fully deterministic behavior of a memory protection unit.

Paper Structure

This paper contains 6 sections, 2 equations, 5 figures, 2 tables.

Figures (5)

  • Figure 1: Two level physical memory protection b3
  • Figure 2: Physical memory protection from the perspective of a hypervisor
  • Figure 3: hPMP hpmpoffsetx register layout, RV32
  • Figure 4: Address map with resizing feature
  • Figure 5: Address map with two virtual machines using generic images