Fast Thermal-Aware Chiplet Placement Assisted by Surrogate
Qinqin Zhang, Xiaoyu Liang, Ning Xu, Yu Chen
TL;DR
This work tackles thermal-aware chiplet placement in 2.5D packaging by introducing TACPAs, a surrogate-assisted simulated annealing framework that uses radial basis function networks to predict the maximum temperature and guides a two-stage optimization prioritizing wirelength/area first and temperature second. It combines global/local RBFN surrogates with occasional high-fidelity HotSpot checks and MILP-based wirelength estimation to dramatically reduce evaluation time while preserving solution quality. Across three real-system cases, TACPAs achieves competitive or superior wirelength with parity or minor improvements in peak temperature relative to baselines, and it demonstrates substantially reduced thermal-simulation cost. This surrogate-based approach enables faster, more scalable design iterations for thermal-aware chiplet placement in 2.5D packages, potentially accelerating agile 2.5D chipset development.
Abstract
With the advent of the post-Moore era, the 2.5-D advanced package is a promising solution to sustain the development of very large-scale integrated circuits. However, the thermal placement of chiplet, due to the high complexity of thermal simulation, is very challenging. In this paper, a surrogate-assisted simulated annealing algorithm is proposed to simultaneously minimize both the wirelength and the maximum temperature of integrated chips. To alleviate the computational cost of thermal simulation, a radial basis function network is introduced to approximate the thermal field, assisted by which the simulated annealing algorithm converges to the better placement in less time. Numerical results demonstrate that the surrogate-assisted simulated annealing algorithm is competitive to the state-of-the-art thermal placement algorithms of chiplet, suggesting its potential application in the agile design of 2.5D package chip.