WebRISC-V: A 64-bit RISC-V Pipeline Simulator for Computer Architecture Classes

TL;DR

The paper addresses the challenge of teaching pipeline behavior in RV64IM by introducing WebRISC-V, a web-based, cycle-accurate simulator that visualizes pipeline execution, stalls, hazards, and forwarding. The approach emphasizes browser-based accessibility, interactive state visualization, and automatic diagram generation to enhance understanding of instruction dependencies and bottlenecks. Key contributions include a fully web-based, cycle-accurate tool with editable instructions, mode switching for forwarding, and comparative workflow features that distinguish it from existing visualizers. This work is significant for education and collaborative research, lowering access barriers and providing precise, interactive insights into RISC-V pipeline dynamics.

Abstract

WebRISC-V is a web-based educational tool designed to simulate the pipelined execution of assembly programs according to the RV64IM specifications (64-bit RISC-V processor). The tool allows users to investigate pipeline stalls, understand the internal state of pipeline architectural blocks, and visualize the cycle-by-cycle execution of instructions. WebRISC-V executes directly in a web browser, providing a detailed pipeline execution for RISC-V processors. This paper describes the features of WebRISC-V, compares it with similar tools, and provides an example of its usage in investigating the pipeline.

Figures (2)

• Figure 1: WebRISC-V main page.
• Figure 2: Pipeline diagram in both visualization methods: (a) 'Full loops' and (b) 'squashed loops'.