HiAER-Spike: Hardware-Software Co-Design for Large-Scale Reconfigurable Event-Driven Neuromorphic Computing

TL;DR

The paper tackles the lack of scalable hardware/software platforms for large-scale, event-driven SNNs. It introduces HiAER-Spike, an FPGA-based hardware-software co-design with hierarchical address-event routing, sparse connectivity storage in HBM, and a Python API integrated with the NSG portal for remote access. Key contributions include a scalable six-server FPGA cluster capable of 160M neurons and 40B synapses, an adjacency-list storage scheme, network partitioning across hardware, and an end-to-end inference workflow with hardware and software simulators. The platform provides a public, low-barrier entry point for researchers to deploy and test large SNNs, enabling low-latency, energy-efficient event-driven computation and potential pathways toward ultra-low-power neuromorphic accelerators and closer integration with AI workflows.

Abstract

In this work, we present HiAER-Spike, a modular, reconfigurable, event-driven neuromorphic computing platform designed to execute large spiking neural networks with up to 160 million neurons and 40 billion synapses - roughly twice the neurons of a mouse brain at faster-than real-time. This system, which is currently under construction at the UC San Diego Supercomputing Center, comprises a co-designed hard- and software stack that is optimized for run-time massively parallel processing and hierarchical address-event routing (HiAER) of spikes while promoting memory-efficient network storage and execution. Our architecture efficiently handles both sparse connectivity and sparse activity for robust and low-latency event-driven inference for both edge and cloud computing. A Python programming interface to HiAER-Spike, agnostic to hardware-level detail, shields the user from complexity in the configuration and execution of general spiking neural networks with virtually no constraints in topology. The system is made easily available over a web portal for use by the wider community. In the following we provide an overview of the hard- and software stack, explain the underlying design principles, demonstrate some of the system's capabilities and solicit feedback from the broader neuromorphic community.

Figures (4)

• Figure 1: High-level system architecture of HiAER-Spike. (a) Neurons and synapses form the 'grey matter' of dense local interconnects in the system while long-range connections (between cores and FPGAs) form the 'white matter' of sparse global interconnects. (b) The hardware equivalent of (a) as implemented in our multi-core architecture on the FPGA. The grey matter inside each core is implemented as sequentially updated integrate-and-fire neurons, whose internal state is stored in neural membrane registers in URAM, whereas spike events are routed through synaptic look-up tables in HBM. The white matter is implemented as a hierarchical multicast bus (HiAER) interconnecting axon spike register modules that are stored in BRAM across cores.
• Figure 2: (a) Host programming interface with SNN compiler and low-level hardware interface. (b) Heterogeneous memory organization within a single core, as well as the off-chip HBM storing the synaptic connectivity table. On-chip URAM and BRAM store state variables of axons and neurons. The top-left panel shows the layout of the data structure in HBM, supporting parallelism of 16 neurons per single core.
• Figure 3: Example network and generating code
• Figure 4: Simplified flowchart describing the process of mapping a network into HBM.