Optimizing Quantum Circuits via ZX Diagrams using Reinforcement Learning and Graph Neural Networks
Alexander Mattick, Maniraman Periyasamy, Christian Ufrecht, Abhishek Y. Dubey, Christopher Mutschler, Axel Plinge, Daniel D. Scherer
TL;DR
The paper tackles quantum circuit optimization under noise by combining ZX-calculus, graph neural networks, and reinforcement learning to learn rule sequences that minimize $CNOT$ gates. It formulates ZX graph rewriting as an RL problem on ZX diagrams, using a tree search and PPO-based training to predict rule applications and positions, with extraction integrated via graph-like ZX diagrams. The approach demonstrates competitive improvements over state-of-the-art, generalizes to unseen gate ratios, and scales to larger circuits through peephole optimization, albeit with slower runtime. This work highlights a path toward discovering optimization rules beyond hand-crafted templates, enabling scalable, diagrammatic circuit optimization suitable for NISQ devices.
Abstract
Quantum computing is currently strongly limited by the impact of noise, in particular introduced by the application of two-qubit gates. For this reason, reducing the number of two-qubit gates is of paramount importance on noisy intermediate-scale quantum hardware. To advance towards more reliable quantum computing, we introduce a framework based on ZX calculus, graph-neural networks and reinforcement learning for quantum circuit optimization. By combining reinforcement learning and tree search, our method addresses the challenge of selecting optimal sequences of ZX calculus rewrite rules. Instead of relying on existing heuristic rules for minimizing circuits, our method trains a novel reinforcement learning policy that directly operates on ZX-graphs, therefore allowing us to search through the space of all possible circuit transformations to find a circuit significantly minimizing the number of CNOT gates. This way we can scale beyond hard-coded rules towards discovering arbitrary optimization rules. We demonstrate our method's competetiveness with state-of-the-art circuit optimizers and generalization capabilities on large sets of diverse random circuits.
